由于电路设计错误，在设计LCMXO3L-6900C-6BG256C的时候,
DCK引脚使用了A9引脚.
刚刚编译发现了一堆错误:
ERROR - Cannot place PIO comp "DCK" on PIO site "A9/PT22C" (I/O bank 0).
ERROR - Cannot place PIO comp "DCK" on the proposed PIO site "PT22C / A9" because the types of their IOLOGICs are incompatible:
the associated IOLOGIC comp "DCK_MGIOL" has been set to "ODDR4" mode (of type "TIOLOGIC"), while the IOLOGIC site is of type "TSIOLOGIC".
ERROR - Please check the pin locking in your preference file.
其实只要不用A9,其他的引脚都可以的，:'(
现在看来有两个办法：
1）重新设计，投板.....
2）有没有办法把oddr的输出通过内部布线连接到A9呢，哪位高手有建议？
环境是Lattice diamond 3.7
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