错误怎么找啊？

只看该作者 · 2016-3-8 21:28

module srcn(clk,rst_n);

input clk,rst_n;
reg[63:0] sc1,ac1,tc,tc1,s1;
reg[63:0] pd [1:255][1:255];
//reg[31:0] nq[0:1];

integer i,j,k,l;

always @(posedge clk or negedge rst_n);
begin
   for(i=1;i<255;i=i+1)
      begin
         for(j=1;j<255;j=j+1)
            begin
            ac1=64'b0;
            tc=64'b0;
            sc1=64'b0;
               for(k=0;k<=2;k=k+1)
                  begin
                     for(l=0;l<=2;l=l+1)
                        begin
                        ac1=ac1+pd[i+k][j+l];
                        end
                  end
  for(k=0;k<=2;k=k+1)
   begin
   for(l=0;l<=2;l=l+1)
         begin
         tc1=pd[i+k][j+l]-ac1;
         tc=tc+pd[i+k][j+l]*tc1;
         end
end
  begin : block1
   reg[31:0] nq;
      for(i=0;i<2;i=i+1)
      nq[i]=32'b0;
  end
      s1=tc/9;
   sc1=s1**(1/2);

if(sc1<1.5)

   begin
   nq[0]=nq[0]+1;
end
else
begin
   nq[1]=nq[1]+1;
end
end
end
end
endmodule
这是原程序，编译之后出现的错误，不知道怎么改，望大神们指点，谢谢!
Error (10170): Verilog HDL syntax error at srcn.v(12) near text "begin";  expecting "endmodule"
Error (10170): Verilog HDL syntax error at srcn.v(50) near text "=";  expecting ".", or an identifier
Error (10112): Ignored design unit "srcn" at srcn.v(1) due to previous errors