imx6Q DDR2(528M) Kernel crash

只看该作者 · 2016-3-29 17:08

IMX6Q (6D) DDR2 528M Kernel crash, 通过DDR STRESS测试，另外DDR400稳定。

DDR2 528 Kernel随机CRASH。

Kernel panic - not syncing: Attempted to kill the idle task!
CPU0: stopping
CPU: 0 PID: 1 Comm: swapper/0 Tainted: G D 3.10.53 #33
[<80014008>] (unwind_backtrace+0x0/0xf8) from [<80011934>] (show_stack+0x10/0x14)
[<80011934>] (show_stack+0x10/0x14) from [<80013254>] (handle_IPI+0x178/0x1a4)
[<80013254>] (handle_IPI+0x178/0x1a4) from [<800085a4>] (gic_handle_irq+0x54/0x5c)
[<800085a4>] (gic_handle_irq+0x54/0x5c) from [<8000dd00>] (__irq_svc+0x40/0x70)
Exception stack(0xa4075af0 to 0xa4075b38)
5ae0: 00000002 00000002 00000002 00000001
5b00: a4075b5c 826104c0 00000001 826104c0 01740000 826104c8 00000001 00000000
5b20: 00000002 a4075b38 8032c3f0 800760bc 20000113 ffffffff
[<8000dd00>] (__irq_svc+0x40/0x70) from [<800760bc>] (generic_exec_single+0x6c/0x90)
[<800760bc>] (generic_exec_single+0x6c/0x90) from [<800761d8>] (smp_call_function_single+0xf8/0x1c0)
[<800761d8>] (smp_call_function_single+0xf8/0x1c0) from [<80076718>] (smp_call_function+0x34/0x68)
[<80076718>] (smp_call_function+0x34/0x68) from [<8007678c>] (on_each_cpu+0x28/0x70)
[<8007678c>] (on_each_cpu+0x28/0x70) from [<80013a70>] (twd_rate_change+0x24/0x30)
[<80013a70>] (twd_rate_change+0x24/0x30) from [<80050158>] (notifier_call_chain+0x44/0x84)
[<80050158>] (notifier_call_chain+0x44/0x84) from [<800502e4>] (__srcu_notifier_call_chain+0x44/0x60)
[<800502e4>] (__srcu_notifier_call_chain+0x44/0x60) from [<80050318>] (srcu_notifier_call_chain+0x18/0x20)

只看该作者 · 2016-3-30 08:54

我记得文档好像有说最大支持400M，你可以确认下～

只看该作者 · 2016-3-30 09:39

imx6q (6D) ?

只看该作者 · 2016-3-30 13:24

是的，你看下datasheet确认下～

只看该作者 · 2016-3-30 14:26

kris_fei 发表于 2016-3-30 13:24
是的，你看下datasheet确认下～

没有看到限制。

只看该作者 · 2016-3-31 16:42

•MMDC running at up to 400 MHz (800MT/s), see CCM block for actual clock
frequencies supported.

只看该作者 · 2016-4-7 15:11

kris_fei 发表于 2016-3-31 16:42
•MMDC running at up to 400 MHz (800MT/s), see CCM block for actual clock
frequencies supported.

i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015

没有搜索到。

只看该作者 · 2016-4-7 15:13

kris_fei 发表于 2016-3-31 16:42
•MMDC running at up to 400 MHz (800MT/s), see CCM block for actual clock
frequencies supported.

DDR performance • MMDC running at up to 528 MHz (1056MT/s), see CCM block for actual clock
               frequencies supported.
            • Supports Real-Time priority by means of QoS sideband priority signals from the chip to
               enable various priority levels in the re-ordering mechanism: real-time, latency sensitive,
            normal priority.
            • Page hit/page miss optimizations
            • Consecutive read/write access optimizations
               • Supports deep read and write request queues to enable bank prediction.
               • Drives back the critical word in a read transaction as soon as it is received by the DDR
               device (does not wait until the whole data phase has been completed).
               • Keeps tracking of open memory pages
               • Supports bank interleaving
                  • Special optimization in case of non-aligned wrap accesses in DDR3 mode (burst length
                  8)
NOTE: Due to reordering and optimization mechanisms (per different AXI Identifier (ID)), the
transactions towards the DDR device may be driven in a different ID order than was
received by the AXI master. In a similar fashion, the write response, read response
or read data may be driven to the AXI master in a different ID order.

只看该作者 · 2016-5-4 09:41

只调过几个型号的ddr3，还真没调过ddr2，关注一下，学习学习......

imx6Q DDR2(528M) Kernel crash

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