DDR performance • MMDC running at up to 528 MHz (1056MT/s), see CCM block for actual clock
frequencies supported.
• Supports Real-Time priority by means of QoS sideband priority signals from the chip to
enable various priority levels in the re-ordering mechanism: real-time, latency sensitive,
normal priority.
• Page hit/page miss optimizations
• Consecutive read/write access optimizations
• Supports deep read and write request queues to enable bank prediction.
• Drives back the critical word in a read transaction as soon as it is received by the DDR
device (does not wait until the whole data phase has been completed).
• Keeps tracking of open memory pages
• Supports bank interleaving
• Special optimization in case of non-aligned wrap accesses in DDR3 mode (burst length
8)
NOTE: Due to reordering and optimization mechanisms (per different AXI Identifier (ID)), the
transactions towards the DDR device may be driven in a different ID order than was
received by the AXI master. In a similar fashion, the write response, read response
or read data may be driven to the AXI master in a different ID order.
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