还有就是手册上关于AD时钟是由PCLK2来的，
The ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must
not exceed 14MHz, refer to Figure8: Clock tree for low-, medium- and high-density devices,
and to Figure11: Clock tree for connectivity line devices.
可是我看Figure8: Clock tree觉得不太对啊！看图AD应当由
APB2 Prescaler到ADC Prescaler然后由ADCCLK得到啊！ 不知道是我哪里理解错了？
楼主
标题置顶
标题高亮
