求救 MAX+plus II 转 Quartus II 9.1 问题

只看该作者 · 2009-11-24 21:12

architecture bhv of ADMODEL is
CONSTANT ST0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
CONSTANT ST1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
CONSTANT ST2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
CONSTANT ST3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00011";
CONSTANT ST4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100";
CONSTANT ST5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00101";
CONSTANT ST6 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110";
CONSTANT ST7 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00111";
CONSTANT ST8 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01000";
CONSTANT ST9 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01001";
CONSTANT ST10 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01010";
CONSTANT ST11 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01011";
CONSTANT ST12 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01100";
CONSTANT ST13 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01101";
CONSTANT ST14 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01110";
CONSTANT ST15 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01111" ;
CONSTANT ST16 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10000";
CONSTANT ST17 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
CONSTANT ST18 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10010";
CONSTANT ST19 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10011";
CONSTANT ST20 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10100";
CONSTANT ST21 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10101";
CONSTANT ST22 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10110";
CONSTANT ST23 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10111";
CONSTANT ST24 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11000";
CONSTANT ST25 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11001";
CONSTANT ST26 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11010";
CONSTANT ST27 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11011";
CONSTANT ST28 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100";
CONSTANT ST29 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11101";
CONSTANT ST30 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11110";
CONSTANT ST31 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11111" ;
TYPE STATES IS ( ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7,ST8,ST9,ST10,ST11,ST12,ST13,ST14,ST15,ST16,ST17,ST18,ST19,ST20,ST21,ST22,ST23,ST24,ST25,ST26,ST27,ST28,ST29,ST30,ST31);
SIGNAL CURRENT_ST,NEXT_ST : STATES;

只看该作者 · 2009-11-24 21:13

在 Quartus II 9.1 里把红色部分去掉就OK了!!!!

只看该作者 · 2009-11-24 21:35

Error (10465): VHDL error at admodel.vhd(59): name "ST0" cannot be used because it is already used for a previously declared item

只看该作者 · 2009-11-26 22:33

SIGNAL CURRENT_ST,NEXT_ST :STD_LOGIC_VECTOR(4 DOWNTO 0);

只看该作者 · 2009-11-28 18:05

楼上的朋友，我看你说的也有一点不对，看他的部分程序，我想他的设计是一个FSM状态机的设计。你把信号定义成位类型是不对的。楼主，你的问题就是，理解错状态编码了。常用是在系统复位时就是编码。而不是设成常量。顺便说一下，你的编码。一般FPGA用独热编码，而CPLD用格雷编码。常常不用二制编码，这样的话很浪费资源的。

只看该作者 · 2009-11-29 17:16

谢谢LS 偶用的是CPLD

求救 MAX+plus II 转 Quartus II 9.1 问题

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