见我之前的贴子《请教新唐的“语音编解码”芯片有中文手册吗？》
https://bbs.21ic.com/icview-1445710-1-1.html
由于确认是没有中文的，于是自己动手，丰衣足食.....
 但到了几个关键段，我真的没法看得明白，虽然我也有在网上搜索相关的知识（如PCM、A-law和u-law）但**一串起来，根本就读不顺畅，无法看懂是啥意思。
因此希望大家能帮帮忙，翻译或讲解一下下面几段文的意思，等我能把这文翻译完成。（到时再分享给大家。）
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync.
The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal.
It recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin.
The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 sec.
During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted.
The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted.
The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state.
More detailed timing information can be found in the interface timing section.
其实我自己已试翻译了一段...呃，大家看不看得明白？
长或短帧同步接口模式可通过连接器BCLKR或BCLKT引脚从64Khz到4.096Mhz的时钟频率来选择，或连接FSR或FST引脚8kHz同步选择。
该装置同步PCM接口和帧同步信号的上升沿采样率的数据字的编解码器。
它长帧同步时，FST引脚保持连接两个下降沿的位时钟在BCLKT引脚高。
帧同步脉冲的长度可以变化从帧到帖，只要积极帖同步边缘发生每隔120秒。
在长帖同步模式下的数据传输过程中，发送数据引脚PCMT将成为低阻搞时的帧同步信号的FST高或当8位数据字被传送。
内部决策逻辑将确定下一帧的同步是否是长或短帧同步，根据前一帖同步脉冲。
为了避免总线冲突的状态下，将每个电源引脚PCMT后两帧同步周期的高阻抗。
更详细的时间信息可以在界面的时间段找到。
———————————————分界线———————————————————————————
7.4.2. Short Frame Sync
The W681512 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin.
On the following rising edge of the bit-clock, the W681512 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state.
The data transmit pin PCMT will go back to the high impedance state halfway through the LSB.
The Short Frame Sync operation of the W681512 is based on an 8-bit data word.
When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal.
The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state.
More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame sync cycles.
It can be used as a 2B+D timing interface in an ISDN application.
The GCI interface consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR).
The FSR pin selects channel B1 or B2 for transmit and receive.
Data transitions occur on the positive edges of the data clock DCL.
The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock.
The channels B1 and B2 are transmitted consecutively.
Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles of DCL.
For more timing information, see the timing section.
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame sync cycles.
It can be used as a 2B+D timing interface in an ISDN application.
The IDL interface consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR).
The FSR pin selects channel B1 or B2 for transmit and receive.
The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC pulse.
The IDL SYNC pulse is one IDL CLK cycle long.
The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC pulse.
The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC pulse.
The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL SYNC pulse.
The transmit signal pin IDL TX becomes high impedance when not used for data transmission and also in the time slot of the unused channel.
For more timing information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz master clock rates.
The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired.
An internal pre-scaler is used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC.
The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly.
If the Frame Sync is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681512 will enter the low power standby mode.
Another way to power down is to set the PUI pin to LOW.
When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame Sync pulse needs to be present.
It will take two Frame Sync cycles before the pin PCMT will become low impedance.
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