程序为：
module ALU(out,select,a,b);
reg[4:0] out;
wire[2:0] select;
wire[3:0] a,b;
input select,a,b;
output out;
always @(a or b )
begin
case(select)
3'b000: out=a;
3'b001: out=a+b;
3'b010: out=a-b;
3'b011: out=a/b;
3'b100: out=a%b;
3'b101: out=a<<1;
3'b110: out=a>>1;
3'b111: out=a>b;
default: out=5'bz;
endcase
end
endmodule
当a,b改为reg型时综合结果是不一样的，求助！！！
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