各位高手救命啊，郁闷死了，帮帮我吧

只看该作者 · 2010-1-3 22:38

module cpuRamPort( clk,pRs,pCs,pRd,pWr,pBus,rAddr,rBus,rCs,rWr,rRd,rgb );
input clk;
input pRs/* synthesis syn_noclockbuf = 1*/;
input pCs/* synthesis syn_noclockbuf = 1*/;
input pRd/* synthesis syn_noclockbuf = 1*/;
input pWr/* synthesis syn_noclockbuf = 1*/;
inout [7:0] pBus;
output [16:0] rAddr;
inout [7:0] rBus;
output reg rCs,rWr,rRd;
output reg [7:0] rgb;
reg [16:0] portAddr;
reg [7:0] portData;
reg [7:0] ramData;
reg [3:0] insReg;
reg [1:0] stat;
reg portNew,ramAck;
assign pBus = ({pRs,pCs,pRd}==3'b100)?ramData:8'hzz;
always @( posedge ramAck or posedge pWr )
begin
      if( ramAck )
      begin
         portNew = 0;
         portAddr = portAddr+1;
      end
      else
      begin
         if( pCs==0 )
         begin
            if( pRs==0 )
                  insReg = pBus[3:0];
            else
            begin
                  case(insReg)
                  4'h0:portAddr[7:0] = pBus;
                  4'h1:portAddr[15:8] = pBus;
                  4'h2:begin
                        portData = pBus;
                        portNew = 1;
                     end
                  4'h5:portAddr[16] = pBus[0];
                  endcase
            end
         end
      end
end
assign rAddr = portAddr;
assign rBus = ( rCs==0 && rWr==0 )? portData:8'hzz;
always @ ( posedge clk )
begin
      case(stat)
      2'b00:
         begin
            rgb = rBus;
            rRd = 1;
            rWr = 1;
            rCs = 1;
            stat = 2'b01;
         end
      2'b01:
         begin
            rCs = 0;
            if( portNew )
            begin
                  ramAck = 1;
                  rWr = 0;
                  rRd = 1;
            end
            else
            begin
                  ramAck = 0;
                  rWr = 1;
                  rRd = 0;
            end
            stat = 2'b10;
         end
      2'b10:
         begin
            if( !ramAck )ramData = rBus;
            rWr = 1;
            rRd = 1;
            rCs = 1;
            stat = 2'b11;
         end
      2'b11:
         begin
            ramAck = 0;
            rWr = 1;
            rRd = 0;
            rCs = 0;
            stat = 2'b00;
         end
      default:stat = 2'b00;
      endcase
end
endmodule

这段代码前仿真一点问题也没有，但是synthesis后再仿真就不正确了，什么原因呢？是代码问题
还是synthsis工具问题，我是初学者不知到底怎么回事，高手们帮帮忙，把代码拷贝到你的机器上
试一下啊，最好把前仿真与后仿真的波形拷贝下来发到论坛上，帮忙啊。。。。