# Reading C:/Actel/Libero_v8.5/Model/tcl/vsim/pref.tcl
# do run.do
# INFO: Simulation library presynth already exists
# Modifying modelsim.ini
# Modifying modelsim.ini
# Model Technology ModelSim ACTEL vlog 6.4a Compiler 2008.08 Aug 29 2008
# -- Compiling module RW_RAM
#
# Top level modules:
# RW_RAM
# Model Technology ModelSim ACTEL vlog 6.4a Compiler 2008.08 Aug 29 2008
# -- Compiling module RAM1
#
# Top level modules:
# RAM1
# Model Technology ModelSim ACTEL vlog 6.4a Compiler 2008.08 Aug 29 2008
# -- Compiling module top
#
# Top level modules:
# top
# Model Technology ModelSim ACTEL vlog 6.4a Compiler 2008.08 Aug 29 2008
# -- Compiling module test_top
#
# Top level modules:
# test_top
# vsim -L igloo -L presynth -t 1ps presynth.testbench
# ** Error: (vsim-3170) Could not find 'G:\Actelwork\balise_actel\simulation\presynth.testbench'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 17 |
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