关于stm32f030f4p6芯片的HSE问题

只看该作者 · 2016-7-12 15:50

本帖最后由 liaojunhui 于 2016-7-12 22:20 编辑

各位大神，最近用stm32f030f4p6这款芯片时遇到一个问题，想要使用外部12MHz的晶振，但是却一直检测不到HSERDY位置1.
程序卡在了下面这一句
while(!HSEStatus)
{
HSEStatus = RCC->CR & RCC_CR_HSERDY; //¼ì²âÍâ²¿HSEÊÇ·ñÆðÕñ£¬µÈ´ýÆðÕñ
}，
哪位大神能帮忙看看，芯片也换过了，12MHz的晶振用示波器也能看到12MHZ的方波。
（不知道上传代码，那段代码就和启动代码段的时钟配置是一样的）
void system_config(void)
{
  uint32_t HSEStatus = 0;
  RCC_DeInit();
  RCC->CR &=0xfffeffff;       //关闭HSE
  RCC->CR |=0x00040000;       //使用外部有源晶振，所以置位该位，旁路HSE，在该模式下，OSC-IN需要外部时钟源，OSC_OUT不接且不能作为IO管脚
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);    //开启HSE外部时钟
  while(!HSEStatus)
{
HSEStatus = RCC->CR & RCC_CR_HSERDY; //检测外部HSE是否起振，等待起振
  }
  if ((RCC->CR & RCC_CR_HSERDY) != RESET)    //外部时钟已起振
  {
HSEStatus = (uint32_t)0x01;
  }
  else
  {
HSEStatus = (uint32_t)0x00;
  }

  if (HSEStatus == 0x01)
  {
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;

/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; //SYSCLK=HCLK,不分频

/* PCLK = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

/* PLL configuration = HSE * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));    //此语句相当于先复位这三个数据
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL4);  //此处改成4倍频，HSE=12MHz

/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;    //开启PLL锁相环

/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0) //等待PLL锁相环开启
{
}

/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
  }
  else
  {
//while(1);
  /* If HSE fails to start-up, the application will have wrong clock
      configuration. User can add here some code to deal with this error */
  }
}