代码可以编译，仿真时波形全是直线，师兄说时钟信号（top-clk）没有启动，导致加密算法未启动，要在生成的test bench中修改testbench如下
// Verilog Test Bench template for design : top
//
// Simulation tool : ModelSim (Verilog)
//
`timescale 1 ps/ 1 ps
module top_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg handshake;
reg [0:127] key;
reg last;
reg top_clk;
reg [0:127] top_datain;
reg [0:1] top_opcode;
reg top_rst;
// wires
wire top_data_complete;
wire [0:127] top_dataout;
wire top_rk_complete;
// assign statements (if any)
top i1 (
// port map - connection between master ports and signals/registers
.handshake(handshake),
.key(key),
.last(last),
.top_clk(top_clk),
.top_data_complete(top_data_complete),
.top_datain(top_datain),
.top_dataout(top_dataout),
.top_opcode(top_opcode),
.top_rk_complete(top_rk_complete),
.top_rst(top_rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
希望大神帮忙处理一下，本人真诚希望与大神交流学习，qq2206638817
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