仿真的错误分析

只看该作者 · 2010-3-27 21:27

Loading presynth.testbench
# ** Error: (vsim-3033) C:/FPGA/get_add0/component/work/get_add00/testbench.v(55): Instantiation of 'get_add00' failed. The design unit was not found.
#       Region: /testbench
#       Searched libraries:
#          C:\Actel\Libero_v9.0\Designer\lib\modelsim\precompiled\vlog\proasic3
#          C:\FPGA\get_add0\simulation\presynth
#          C:\FPGA\get_add0\simulation\presynth
# Error loading design
# Error: Error loading design
#       Pausing macro execution

请问这是什么错误？谢啦