1、首先是stm32f10x.h中的HSE_VALUE[cpp] view plain copy
- #if !defined HSE_VALUE
- #ifdef STM32F10X_CL
- #define HSE_VALUE ((uint32_t)12000000)//这里修改为12MHz
- // #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */注释掉
- #else
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* STM32F10X_CL */
- #endif /* HSE_VALUE */
2、修改分频/倍频系数使系统时钟变为72MHz
在system_stm32f10x.c的void SystemInit (void)函数下有一个SetSysClock()继续找static void SetSysClock(void)下的SetSysClockTo72();修改后如下一段代码:
其中被注释掉的部分为原来的代码。
[cpp] view plain copy
- <pre name="code" class="cpp"> /* Configure PLLs ------------------------------------------------------*/
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
- // RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
- // RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-
- //HSE = 12 PLL2CLK = (HSE / 3) * 10 = 40 MHz
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV3 | RCC_CFGR2_PLL2MUL10 |
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
- /* Enable PLL2 */
- RCC->CR |= RCC_CR_PLL2ON;
- /* Wait till PLL2 is ready */
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)
- {
- }
-
- //
- // /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- // RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- // RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- // RCC_CFGR_PLLMULL9);
-
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
- RCC_CFGR_PLLMULL6);
- #else
- // /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- // RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- // RCC_CFGR_PLLMULL));
- // RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-
-
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
- RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
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