EPwm1Regs.CMPCTL.all=0x50; // Immediate mode for CMPA and CMPB
EPwm1Regs.CMPA.half.CMPA =SP/4;
EPwm1Regs.CMPB=SP/4;
EPwm1Regs.AQCTLA.all=0x60; // EPWMxA = 1 when CTR=CMPA and counter inc
// EPWMxA = 0 when CTR=CMPA and counter dec
EPwm1Regs.AQCTLB.all=0x60;
// EPwm1Regs.AQCTLB.all=0;
EPwm1Regs.AQSFRC.all=0;
EPwm1Regs.AQCSFRC.all=0;
EPwm1Regs.DBCTL.all=0x23; // EPWMxB is inverted
EPwm1Regs.DBRED=0;
EPwm1Regs.DBFED=0;