EmBITZ没有Nnuvoton CM0芯片向导，虽然可以使用NXP等公司的CM0芯片生成工程向导，但startup_ARMCM0.s启动文件还是需要修改的，其他这些芯片的外部中断向量表不一定相同，所以一定需要根据芯片技术资料进行修改。对于GPIO例程而言，没有中断函数，按照作者提供的文件就可以实现LED的闪烁。但对于需要使用中断的C函数，有点儿讨厌。在startup_ARMCM0.s文件中配置中断向量表就非常必要了。
作者根据新唐官方TRM_051(DN_DE)_Series_EN_Rev1.02配置的startup_ARMCM0.s启动文件如下，请测试。有问题，请反馈。
/************************************************************************************
* File: startup.S
* Purpose: Startup file for Cortex-M0/0+/1 devices.
* Should use with GCC for ARM Embedded Processors
* Version: V1.4
* Date: 09 July 2012
* Notice: Changed for use with emIDE project wizard
* Date: 05 July 2013
*
* Copyright (c) 2011, 2012, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the ARM Limited nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
************************************************************************************/
.syntax unified
.arch armv6-m
/************************************************************************************
*
* The minimal vector table for Cortex-M3.
* Device specific external interrupts can be added below.
************************************************************************************/
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __stack_end__ /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */ //如果为作者添加的
//.long Default_Handler
.long BOD_IRQHandler /* 0: Brown-out low */
.long WTD_IRQHandler /* 1: Watchdog Timer*/
.long EINT0_IRQHandler /* 2: External signal interrupt 0 */
.long EINT1_IRQHandler /* 3: External signal interrupt 1*/
.long GP01_IRQHandler /* 4: External signal interrupt from P0/P1 */
.long GP234_IRQHandler /* 5: External signal interrupt from P2/P3 */
.long PWMA_IRQHandler /* 6: PWM0~3 interrupt */
.long PWMB_IRQHandler /* 7: PWM4~7 interrupt */
.long TMR0_IRQHandler /* 8: Timer 0 interrupt */
.long TMR1_IRQHandler /* 9: Timer 1 interrupt */
.long TMR2_IRQHandler /* 10: Timer 2 interrupt */
.long TMR3_IRQHandler /* 11: Timer 3 interrupt */
.long UART0_IRQHandler /* 12: UART0 interrupt */
.long UART1_IRQHandler /* 13: UART1 interrupt */
.long SPI0_IRQHandler /* 14: SPI0 interrupt */
.long SPI1_IRQHandler /* 15: SPI1 interrupt */
.long 0 /* 16: Reserved */
.long 0 /* 17: Reserved */
.long I2C0_IRQHandler /* 18: I2C0 interrupt */
.long I2C1_IRQHandler /* 19: I2C1 interrupt */
.long 0 /* 20: Reserved */
.long 0 /* 21: Reserved */
.long 0 /* 22: Reserved */
.long 0 /* 23: Reserved */
.long 0 /* 24: Reserved */
.long ACMP01_IRQHandler /* 25: Analog Comparator 0/1 interrupt */
.long ACMP23_IRQHandler /* 26: Analog Comparator 2/3 interrupt */
.long 0 /* 27: Reserved */
.long PWRWU_IRQHandler /* 28:Clock controller interrupt */
.long ADC_IRQHandler /* 29: ADC interrupt */
.long 0 /* 30: Reserved */
.long 0 /* 31: Reserved */
.size __isr_vector, . - __isr_vector
/************************************************************************************
*
* Reset_Handler()
* This function gets called at start of execution after a reset event.
* Copies data from ROM to RAM, clears BSS if defined,
* calls SystemInit() if defined, finally calls main()
************************************************************************************/
.text
.thumb
.global __stack_end__
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Setup stack pointer. Helpful for targets running in RAM without script file */
ldr r1, =__stack_end__
msr msp, r1
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
/* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
subs r2, r1
ble .LC3
movs r0, 0
.LC2:
str r0, [r1, r2]
subs r2, 4
bge .LC2
.LC3:
#ifndef __NO_SYSTEM_INIT
bl SystemInit //此处定义了SystemInit函数
#endif
bl main
.pool
.size Reset_Handler, . - Reset_Handler
/************************************************************************************
*
* Weak definition for exceptions.
* Any function with the same name will override the weak definition.
************************************************************************************/
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
//def_default_handler Default_Handler
//如果为作者添加的
def_default_handler BOD_IRQHandler /* 0: Brown-out low */
def_default_handler WTD_IRQHandler /* 1: Watchdog Timer*/
def_default_handler EINT0_IRQHandler /* 2: External signal interrupt 0 */
def_default_handler EINT1_IRQHandler /* 3: External signal interrupt 1*/
def_default_handler GP01_IRQHandler /* 4: External signal interrupt from P0/P1 */
def_default_handler GP234_IRQHandler /* 5: External signal interrupt from P2/P3 */
def_default_handler PWMA_IRQHandler /* 6: PWM0~3 interrupt */
def_default_handler PWMB_IRQHandler /* 7: PWM4~7 interrupt */
def_default_handler TMR0_IRQHandler /* 8: Timer 0 interrupt */
def_default_handler TMR1_IRQHandler /* 9: Timer 1 interrupt */
def_default_handler TMR2_IRQHandler /* 10: Timer 2 interrupt */
def_default_handler TMR3_IRQHandler /* 11: Timer 3 interrupt */
def_default_handler UART0_IRQHandler /* 12: UART0 interrupt */
def_default_handler UART1_IRQHandler /* 13: UART1 interrupt */
def_default_handler SPI0_IRQHandler /* 14: SPI0 interrupt */
def_default_handler SPI1_IRQHandler /* 15: SPI1 interrupt */
def_default_handler I2C0_IRQHandler /* 18: I2C0 interrupt */
def_default_handler I2C1_IRQHandler /* 19: I2C1 interrupt */
def_default_handler ACMP01_IRQHandler /* 25: Analog Comparator 0/1 interrupt */
def_default_handler ACMP23_IRQHandler /* 26: Analog Comparator 2/3 interrupt */
def_default_handler PWRWU_IRQHandler /* 28:Clock controller interrupt */
def_default_handler ADC_IRQHandler /* 29: ADC interrupt */
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.end
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