quartus 9分频问题

只看该作者 · 2016-12-21 21:59

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT9 IS
PORT (CLK : IN STD_LOGIC;
K_OR,K1,K2 : OUT STD_LOGIC);
END;
ARCHITECTURE bhv OF CNT9 IS
SIGNAL C1,C2 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL M1,M2 : STD_LOGIC;
BEGIN
PROCESS(CLK,C1)
BEGIN
IF RISING_EDGE(CLK) THEN
IF (C1="1011") THEN C1<="0000"; ELSE C1<=C1+1;END IF;
IF (C1="0001") THEN M1<=NOT M1; ELSIF (C1="0101") THEN M1<=NOT M1;
END IF; END IF;
END PROCESS;
PROCESS(CLK,C2) BEGIN
IF FALLING_EDGE(CLK) THEN
IF (C2="1011") THEN C2<="0000";ELSE C2<=C2+1;END IF;
IF (C2="0001") THEN M2<=NOT M2;ELSIF(C2="0101") THEN M2<=NOT M2;
END IF;END IF;
END PROCESS;
K1<=M1;K2<=M2;K_OR<=M1 OR M2;
END bhv;
看看程序哪里有问题，怎么得出来的高电平和低电平不一样