library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add_sub is
port ( a,b:in std_logic_vector(3 downto 0);
add_subn:in std_logic;
q:out std_logic_vector(4 downto 0);
M:out std_logic_vector(3 downto 0)
);
end add_sub;
architecture a of add_sub is
begin
M <= "0001";
process(a,b,add_subn)
begin
if add_subn='1' then
q<=('0' & a)+b;
else
q<=('0' & a)-b;
end if;
end process;
end a;
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