本帖最后由 ilostid 于 2016-12-30 00:35 编辑
裸奔Beaglebone black， 貌似DDR3初始化成功，但进入DEBUG时报Could not start CPU（如附件图片所示），郁闷，大家给点建议吧，附修改好的AM335X_BBB_DDR3.mac，不过不清楚修改对没。有兴趣的可以试试，看是否会碰到我一样的错误。
JLINK V9
IAR 7.0
点击download and debug 后，初始化IAR输出后打印信息如下：
Fri Dec 30, 2016 00:19:42: Loaded macro file: C:\ti\AM335X_StarterWare_02_00_01_01\tools\ewarm\AM335x_BBB_DDR3.mac
Fri Dec 30, 2016 00:19:43: JLINK command: ProjectFile = C:\ti\AM335X_StarterWare_02_00_01_01\build\armv7a\ewarm\am335x\beaglebone\uart\settings\uartEcho_Debug.jlink, return = 0
Fri Dec 30, 2016 00:19:43: Device "AM3358" selected (0 KB flash, 0 KB RAM).
Fri Dec 30, 2016 00:19:43: DLL version: V4.80g, compiled Feb 13 2014 20:50:02
Fri Dec 30, 2016 00:19:43: Firmware: J-Link V9 compiled Apr 22 2016 11:47:06
Fri Dec 30, 2016 00:19:43: JTAG speed is initially set to: 32 kHz
Fri Dec 30, 2016 00:19:43: Initial reset was performed
Fri Dec 30, 2016 00:19:43: TotalIRLen = 6, IRPrint = 0x01
Fri Dec 30, 2016 00:19:43: TotalIRLen = 10, IRPrint = 0x0011
Fri Dec 30, 2016 00:19:43: ARM AP[0]: 0x04770001, AHB-AP
Fri Dec 30, 2016 00:19:43: ARM AP[1]: 0x04770002, APB-AP
Fri Dec 30, 2016 00:19:43: ARM AP[2]: 0x04760000, JTAG-AP
Fri Dec 30, 2016 00:19:43: Found Cortex-A8 r3p2
Fri Dec 30, 2016 00:19:43: 6 code breakpoints, 2 data breakpoints
Fri Dec 30, 2016 00:19:43: Data endian: little
Fri Dec 30, 2016 00:19:43: Main ID register: 0x413FC082
Fri Dec 30, 2016 00:19:43: L1 (I-cache): 32 KB, 128 sets, LineSize 64 bytes, 4-way
Fri Dec 30, 2016 00:19:43: L1 (D-cache): 32 KB, 128 sets, LineSize 64 bytes, 4-way
Fri Dec 30, 2016 00:19:43: L2 (unified cache): 0 KB, 1 sets, LineSize 256 bytes, 1-way
Fri Dec 30, 2016 00:19:43: System control register:
Fri Dec 30, 2016 00:19:43: Instruction endian: little
Fri Dec 30, 2016 00:19:43: Level-1 instruction cache disabled
Fri Dec 30, 2016 00:19:43: Level-1 data cache disabled
Fri Dec 30, 2016 00:19:43: MMU disabled
Fri Dec 30, 2016 00:19:43: Branch prediction enabled
Fri Dec 30, 2016 00:19:43: Found 2 JTAG devices, Total IRLen = 10:
Fri Dec 30, 2016 00:19:43: #0 Id: 0x3BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Fri Dec 30, 2016 00:19:43: #1 Id: 0x2B94402F, IRLen: 6, IRPrint: 0x1 TI ICEPick
Fri Dec 30, 2016 00:19:44: AM335x EVM-SK Initialization is in progress ..........
Fri Dec 30, 2016 00:19:44: **** Subarctic ALL ADPLL Config for OPP == OPP100 is In Progress .........
Fri Dec 30, 2016 00:19:44: Input Clock Read from SYSBOOT[15:14]: 24MHz
Fri Dec 30, 2016 00:19:44: **** Going to Bypass...
Fri Dec 30, 2016 00:19:44: **** Bypassed, changing values...
Fri Dec 30, 2016 00:19:44: **** Locking ARM PLL
Fri Dec 30, 2016 00:19:44: **** Core Bypassed
Fri Dec 30, 2016 00:19:44: **** Now locking Core...
Fri Dec 30, 2016 00:19:44: **** Core locked
Fri Dec 30, 2016 00:19:44: **** DDR DPLL Bypassed
Fri Dec 30, 2016 00:19:45: **** DDR DPLL Locked
Fri Dec 30, 2016 00:19:45: **** PER DPLL Bypassed
Fri Dec 30, 2016 00:19:45: **** PER DPLL Locked
Fri Dec 30, 2016 00:19:45: **** DISP PLL Config is in progress ..........
Fri Dec 30, 2016 00:19:45: **** DISP PLL Config is DONE ..........
Fri Dec 30, 2016 00:19:45: **** Subarctic ALL ADPLL Config for OPP == OPP100 is Done .........
Fri Dec 30, 2016 00:19:45: **** AM335x OPP120 DDR3 EMIF and PHY configuration is in progress.........
Fri Dec 30, 2016 00:19:45: EMIF PRCM is in progress .......
Fri Dec 30, 2016 00:19:45: EMIF PRCM Done
Fri Dec 30, 2016 00:19:45: DDR PHY Configuration In progress
Fri Dec 30, 2016 00:19:45: GPIO module clock configuration is done .......
Fri Dec 30, 2016 00:19:46: Waiting for VTP Ready .......
Fri Dec 30, 2016 00:19:46: VTP Enable Done
Fri Dec 30, 2016 00:19:46: DDR PHY CMD Register configuration is in progress .......
Fri Dec 30, 2016 00:19:46: DDR PHY CMD Register configuration is in progress .......
Fri Dec 30, 2016 00:19:46: DDR PHY CMD Register configuration is in progress .......
Fri Dec 30, 2016 00:19:46: DDR PHY Data Register configuration is in progress .......
Fri Dec 30, 2016 00:19:46: DDR PHY Data Register configuration is in progress .......
Fri Dec 30, 2016 00:19:47: EMIF Timing register configuration is in progress .......
Fri Dec 30, 2016 00:19:47: EMIF Timing register configuration is done .......
Fri Dec 30, 2016 00:19:47: PHY is READY!!
Fri Dec 30, 2016 00:19:47: DDR PHY Configuration done
Fri Dec 30, 2016 00:19:47: **** AM335x OPP120 DDR3 EMIF and PHY configuration is done.........
Fri Dec 30, 2016 00:19:47: AM335x EVM-SK Initialization is done ..........
Fri Dec 30, 2016 00:19:48: 33592 bytes downloaded (105.14 Kbytes/sec)
Fri Dec 30, 2016 00:19:48: Loaded debugee: C:\ti\AM335X_StarterWare_02_00_01_01\binary\armv7a\ewarm\am335x\beaglebone\uart\Debug\uartEcho.out
Fri Dec 30, 2016 00:19:48: Target reset
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