这个是怎么算的？

1万 · 2017-2-12 22:35

对于这个函数

01. SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |

02. SYSCTL_XTAL_8MHZ);

配置的效果是50MHZ，这个是怎么算的？

1万 · 2017-2-12 22:40

是把8MHZ的外部晶振先倍频到400MHZ，然后再分频

只看该作者 · 2017-2-12 22:44

这个需要看下芯片内部的时钟设置相关寄存器的

只看该作者 · 2017-2-12 22:46

有分频寄存器的也有倍频寄存器的，，最终的结果就是从基础晶振上设计来的

1万 · 2017-2-12 22:47

但是从字面上看是4分频，反推的话就是200MHZ，有点没搞明白。

1万 · 2017-2-12 22:50

再一点就是我想用12MHZ的时候，分不出来这个频率的，不是12.5，就是11.768。

1万 · 2017-2-12 22:53

因为SYSCTL_USE_PLL启用了内部的PLL，它的时钟参考源是外部晶振，PLL额定值是200MHz，SYSCTL_SYSDIV_4将其四分频，所以是50MHz不知道你用哪款芯片，811的话内部有内部振荡器12MHz+-30%

1万 · 2017-2-12 22:55

感觉上这个频率设置还不能低了，我设置17分频和16.5都是11.768左右，以前没在意这个，现在想感觉这块不是很好用

1万 · 2017-2-12 23:02

PLL-400MHz后就进行了一次分频（除2），这时已经是200MHz了，然后才是你写
的分频系数，手册上说了1/2/3分频系数保留，至于保留可能就是不让你这么设，或
者即使你设了也按最大50MHz工作。

1万 · 2017-2-12 23:04

还有你的17和16.5分频是怎么设出来的，设置分频系数总共才4个位，除非你的芯片支持80MHz工作.

1万 · 2017-2-12 23:06

楼上朋友，我说的情况是针对LM3S811的，帖子里已经说明了，截图也出自811的数据手册，至于框图上的200MHz是否是从内部其他400MHz分频来的，我不知道的，我只是初学，呵呵。我猜不是，不然为何框图里不写成400MHz，而且后面的技术参数也不写成400MHz，而是200MHz？

楼主在3楼的截图可能是8000系列的，至少LM3S8962数据手册里头有一模一样的图表，在第183和第184页。楼主你的截图出自哪个芯片的文档？这个问题要看你的具体MCU型号，这个型号你都没弄清楚，不好讨论吧：）

不使用PLL的话，所接外部晶振最高能到8.192MHz。使用PLL，似乎确实无法分频得到精确的12MHz。

准确答案，得请教TI专家！

1万 · 2017-2-12 23:08

不好意思，我很多都没说清除
我用的是LM3S6965
至于说其他的分频，时间紧了点，手册没有仔细通读，只是看了Driver Library的用户手册，看到程序里一些定义
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1       0x07800000  // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2       0x00C00000  // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3       0x01400000  // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4       0x01C00000  // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5       0x02400000  // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6       0x02C00000  // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7       0x03400000  // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8       0x03C00000  // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9       0x04400000  // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10       0x04C00000  // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11       0x05400000  // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12       0x05C00000  // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13       0x06400000  // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14       0x06C00000  // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15       0x07400000  // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16       0x07C00000  // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17       0x88400000  // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18       0x88C00000  // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19       0x89400000  // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20       0x89C00000  // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21       0x8A400000  // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22       0x8AC00000  // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23       0x8B400000  // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24       0x8BC00000  // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25       0x8C400000  // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26       0x8CC00000  // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27       0x8D400000  // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28       0x8DC00000  // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29       0x8E400000  // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30       0x8EC00000  // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31       0x8F400000  // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32       0x8FC00000  // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33       0x90400000  // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34       0x90C00000  // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35       0x91400000  // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36       0x91C00000  // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37       0x92400000  // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38       0x92C00000  // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39       0x93400000  // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40       0x93C00000  // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41       0x94400000  // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42       0x94C00000  // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43       0x95400000  // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44       0x95C00000  // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45       0x96400000  // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46       0x96C00000  // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47       0x97400000  // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48       0x97C00000  // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49       0x98400000  // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50       0x98C00000  // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51       0x99400000  // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52       0x99C00000  // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53       0x9A400000  // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54       0x9AC00000  // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55       0x9B400000  // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56       0x9BC00000  // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57       0x9C400000  // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58       0x9CC00000  // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59       0x9D400000  // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60       0x9DC00000  // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61       0x9E400000  // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62       0x9EC00000  // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63       0x9F400000  // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64       0x9FC00000  // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5    0xC1000000  // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5    0xC1800000  // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5    0xC2000000  // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5    0xC2800000  // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5    0xC3000000  // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5    0xC3800000  // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5    0xC4000000  // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5    0xC4800000  // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5    0xC5000000  // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5    0xC5800000  // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5    0xC6000000  // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5    0xC6800000  // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5    0xC7000000  // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5    0xC7800000  // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5    0xC8000000  // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5    0xC8800000  // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5    0xC9000000  // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5    0xC9800000  // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5    0xCA000000  // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5    0xCA800000  // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5    0xCB000000  // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5    0xCB800000  // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5    0xCC000000  // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5    0xCC800000  // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5    0xCD000000  // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5    0xCD800000  // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5    0xCE000000  // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5    0xCE800000  // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5    0xCF000000  // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5    0xCF800000  // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5    0xD0000000  // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5    0xD0800000  // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5    0xD1000000  // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5    0xD1800000  // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5    0xD2000000  // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5    0xD2800000  // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5    0xD3000000  // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5    0xD3800000  // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5    0xD4000000  // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5    0xD4800000  // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5    0xD5000000  // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5    0xD5800000  // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5    0xD6000000  // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5    0xD6800000  // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5    0xD7000000  // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5    0xD7800000  // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5    0xD8000000  // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5    0xD8800000  // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5    0xD9000000  // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5    0xD9800000  // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5    0xDA000000  // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5    0xDA800000  // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5    0xDB000000  // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5    0xDB800000  // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5    0xDC000000  // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5    0xDC800000  // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5    0xDD000000  // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5    0xDD800000  // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5    0xDE000000  // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5    0xDE800000  // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5    0xDF000000  // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5    0xDF800000  // Processor clock is pll / 63.5

然后我就试验了一下，发现最高只能到50MHZ，17分频不是理论值等情况，可能就是我截图里到12.5MHZ的最低值，到12.5MHZ的时候，感觉跟我在BOOT里用的内部晶振效果差不多，也就没再继续纠结了

1万 · 2017-2-12 23:10

其实如果用库，使能PLL的话，您可以这样简单的理解，可以认为是200Mhz/n，n=1到64之间的整数或整数/2；比如SYSCTL_SYSDIV_4时，是50M；SYSCTL_SYSDIV_2_5就是80M。

12M是无法直接分频得到的，只能使用外部12M晶振得到。

1万 · 2017-2-12 23:17

好像12MHz外部晶振不行吧，看手册说不用PLL时，晶振最高到8.192MHz啊？是这样理解吧？

2万 · 2017-2-12 23:19

tempest和firestorm系列可以，其他的系列不行。

1万 · 2017-2-12 23:21

查查这个参数“SYSCTL_SYSDIV_4”，是他决定的！

2万 · 2017-2-13 11:49

shimx 发表于 2017-2-12 22:40
是把8MHZ的外部晶振先倍频到400MHZ，然后再分频

你怎么知道这是400Mhz的频率？

2万 · 2017-2-13 11:52

这个都是频率倍频然后分频实现。

1万 · 2017-2-13 17:50

结贴了，多谢大家讨论这么多哈，呵呵

这个是怎么算的？

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