源程序是这样的：
module LED(
clk48M, //48M时钟输入
RSTn, //复位信号，高电平复位
LED //LED输出
)；
input clk48M;
input RSTn;
output [3:0] LED;
reg [3:0] LED;
reg [22:0] count; //分频计数器
always@(posedge clk48M or negedge RSTn)
begin
if(!RSTn) //异步复位
begin
LED<=4'h8; //复位后，LED高位点亮
count<=23'h0; //计数器赋初值
end
else
begin
count<=count+1;
if(count==23'hff_ff_ff)
begin
LED<=LED>>1; //LED移位输出
count<=0;
if(LED==4'h0) //LED复位
LED<=4'h8;
end
end
end
endmodule
然后编译就出错了：
File LED.v has been saved.
D:/My Documents/FPGA/LED/hdl/LED.v(5): ERROR: syntax error near ?(VERI-1137)
1 ERROR(S), 0 WARNING(S).
ERROR: The command 'check_hdl' failed.
ERROR: Failure when executing Tcl script. [ Line 1 ]
ERROR: The Execute Script command failed.
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