求助：基于FPGA的矩阵键盘程序

只看该作者 · 2010-4-25 15:32

求助：
FPGA的键盘扫描程序，以下是我用Verilog写的，但出现如下错误
Error (10170): Verilog HDL syntax error at jianpan.v(17) near text "b"; expecting ";"

敢问高手改如何解决啊
module jianpan(clk,hang1,lie1,out);
input clk,hang1,lie1;
output out;
wire[2:0] hang1;
wire[5:0] lie1;
reg[2:0] hang;
reg[5:0] lie;
reg[3:0] out;
integer i,out1,out2,out3;

initial
begin
i=0;
out1=0;
out2=0;
out3=0;
hang1=3b'111; 错误提示在这行
lie1=6b'000000; 这行也有同样的错误
end

initial
begin
hang=hang1;
lie=lie1;
end

always(@posedge clk)
begin
if(hang==3b'111)
out=4b'0000;
else if(out1==0)
begin
lie=6b'011111;
if(hang[0]==1)
lie=6b'101111;
if(hang[0]==1)
lie=6b'110111;
if(hang[0]==1)
lie=6b'111011;
if(hang[0]==1)
lie=6b'111101;
if(hang[0]==1)
lie=6b'111110;
if(hang[1]==1)
lie=6b'011111;
if(hang[1]==1)
lie=6b'101111;
if(hang[1]==1)
lie=6b'110111;
if(hang[1]==1)
lie=6b'111011;
else
out1=4b'1001;
else
out1=4b'1000;
else
out1=4b'0111;
else
out1=4b'0111;
else
out1=4b'0110;
else
out1=4b'0101;
else
out1=4b'0100;
else
out1=4b'0011;
else
out1=4b'0010;
else
out1=4b'0001;
end
end
always(@posedge clk&&out1!=0)
begin
if(hang==3b'111)
out=4b'0000;
else if
lie=6b'011111;
if(hang[0]==1)
lie=6b'101111;
if(hang[0]==1)
lie=6b'110111;
if(hang[0]==1)
lie=6b'111011;
if(hang[0]==1)
lie=6b'111101;
if(hang[0]==1)
lie=6b'111110;
if(hang[1]==1)
lie=6b'011111;
if(hang[1]==1)
lie=6b'101111;
if(hang[1]==1)
lie=6b'110111;
if(hang[1]==1)
lie=6b'111011;

else
out2=4b'1001;
else
out2=4b'1000;
else
out2=4b'0111;
else
out2=4b'0111;
else
out2=4b'0110;
else
out2=4b'0101;
else
out2=4b'0100;
else
out2=4b'0011;
else
out2=4b'0010;
else
out2=4b'0001;
end

always(@posedge clk&&out3==0)
begin
if(hang==3b'111)
out=4b'0000;
else if
lie=6b'011111;
if(hang[0]==1)
lie=6b'101111;
if(hang[0]==1)
lie=6b'110111;
if(hang[0]==1)
lie=6b'111011;
if(hang[0]==1)
lie=6b'111101;
if(hang[0]==1)
lie=6b'111110;
if(hang[1]==1)
lie=6b'011111;
if(hang[1]==1)
lie=6b'101111;
if(hang[1]==1)
lie=6b'110111;
if(hang[1]==1)
lie=6b'111011;
else
out3=4b'1001;
else
out3=4b'1000;
else
out3=4b'0111;
else
out3=4b'0111;
else
out3=4b'0110;
else
out3=4b'0101;
else
out3=4b'0100;
else
out3=4b'0011;
else
out3=4b'0010;
else
out3=4b'0001;
end

always(@posedge clk)
begin
lie=6b'111110;
if(hang[2]==0)
i=i+1;
if(i==1)
out=out1;
else if(i==2)
out=out2;
else if(i==3)
out=out3;