这是打开时的提示：
# Top Level Design Parameters
# Clocks
createe Path Constraints
_clock -period 4.000000 -waveform {0.000000 2.000000} clk_48M
# False Paths Between Clocks
# Fals
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
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楼主
