本帖最后由 A锐捷无法认证 于 2017-3-17 17:51 编辑
问题描述：
发送数据的时候由于TXRDY一直是高电平1，导致进入死循环，我解决的办法是换一颗芯片，然后就能正常读写了，我
不知道什么原因导致的这样？？？ 该函数是库函数，红色就是引起死循环的原因
while (cnt > 0)
{
status = p_twi->TWI_SR;
if (status & TWI_SR_NACK)
{
return TWI_RECEIVE_NACK; //无应答
}
if (!(status & TWI_SR_TXRDY))
{
printf("6666666666666666666666\n");
continue;
}
p_twi->TWI_THR = *buffer++;
cnt--;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet)
{
uint32_t status;
uint32_t cnt = p_packet->length;
uint8_t *buffer = p_packet->buffer;
/* Check argument */
if (cnt == 0)
{
return TWI_INVALID_ARGUMENT;//无效的内容
}
/* Set write mode, slave address and internal address byte lengths */
p_twi->TWI_MMR = 0;
p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) |
((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
TWI_MMR_IADRSZ_Msk);
/* Set internal address for remote chip */
p_twi->TWI_IADR = 0;
p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
/* Send all bytes */
while (cnt > 0)
{
/*
NACK used in Master mode:
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte or an address byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
*/
status = p_twi->TWI_SR;
//TWI_SR_NACK = 1:表示有数据没有写入，TWI_SR_NACK = 0:表示数据成功写入
if (status & TWI_SR_NACK)
{
return TWI_RECEIVE_NACK; //无应答
}
/*
TXRDY used in Master mode:
0: The transmit holding register has not been transferred into internal shifter. Set to 0 when writing into TWI_THR.
1: As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
*/
if (!(status & TWI_SR_TXRDY))
{
printf("6666666666666666666666\n");
continue;
}
p_twi->TWI_THR = *buffer++;
cnt--;
} |
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