本帖最后由 jht123456789 于 2010-5-1 17:02 编辑
1 library ieee;
2 use ieee.std_logic_1164.all;
3 entity top is
4 port(clr:in std_logic;
5 en:in std_logic;
6 a,b,c,d:in std_logic;
7 add:in std_logic;
8 leda,ledb,ledc,ledd：ut std_logic;
9 fa:ut std_logic_vector(3 downto 0);
10 fi:ut std_logic_vector(6 downto 0);
11 sca2,sca1,sca0:ut std_logic_vector(6 downto 0);
12 scb2,scb1,scb0:ut std_logic_vector(6 downto 0);
13 scc2,scc1,scc0:ut std_logic_vector(6 downto 0);
14 scd2,scd1,scd0:ut std_logic_vector(6 downto 0));
15 end top;
16 architecture rtl of top is
17 component opt is
18 port(clr,en:instd_logic;
19 a,b,c,d:in std_logic;
20 leda,ledb,ledc,ledd:ut std_logic;
21 fa,q:ut std_logic_vector(3 downto 0);
22 end component;
23 component counter is
24 port(add:in std_logic;
25 chos:in std_logic_vector(3 downto 0);
26 a2,a1,a0:ut std_logic_vector(3 downto 0);
27 b2,b1,b0:ut std_logic_vector(3 downto 0);
28 c2,c1,c0:ut std_logic_vector(3 downto 0);
29 d2,d1,d0:ut std_logic_vector(3 downto 0));
30 end component;
31 component output is
32 port(din:in_logic_vector(3 downto 0);
33 dount:ut std_logic_vector(6 downto 0);
34 end component;
35 signal q:std_logic_vector(3 downto 0);
36 signal aa2,aa1,aa0:std_logic_vector(3 downto 0);
37 signal bb2,bb1,bb0:std_logic_vector(3 downto 0);
38 signal cc2,cc1,cc0:std_logic_vector(3 downto 0);
39 signal dd2,dd1,dd0:std_logic_vector(3 downto 0);
40 begin
41 u1:pt port map(clr.en,a,b,c,d,leda,ledb,ledc,ledd,fa,q);
42 u2:counter port map(add,q,aa2,aa1,aa0,bb2,bb1,bb0,cc2,cc1,cc0,dd2,dd1,dd0);
43 u3:utput port map(q,fi);
44 u4:utput port map(aa2,sca2);
45 u5:utput port map(aa1,sca1);
46 u6:utput port map(aa0,sca0);
47 u7:utput port map(bb2,scb2);
48 u8:utput port map(bb1,scb1);
49 u9:utput port map(bb0,scb0);
50 u10:utput port map(cc2,scb2);
51 u11:utput port map(cc1,scc1);
52 u12:utput port map(cc0,scc0);
53 u13:utput port map(dd2,scd2);
54 u14:utput port map(dd1,scd2);
55 u15:utput port mao(dd0,scd0);
56 end rtl;
程序出现了这样的错误提示
Error (10500): VHDL syntax error at top.vhd(22) near text "end"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at top.vhd(34) near text "end"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at top.vhd(40) near text "begin"; expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error: Node instance "U1" instantiates undefined entity "opt"
为什么呢？求大家帮忙！ |
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