大家好,这个问题困扰多天,只能求助各位大大了。
配置为SPI模式,发送16个16bit数据,发现数据总是不对,时钟有时候也不对,有时候是16bit,有时18bit,还有15bit,但只发一个数据的时候是正确的。
配置如下:
//*************** RESET MCBSP
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
//McbspaRegs.SPCR1.bit.DLB = 1;
McbspaRegs.SPCR1.bit.CLKSTP = 2; // Low inactive state without delay:
McbspaRegs.PCR.bit.CLKXP = 0; // transmits data on the rising edge
McbspaRegs.PCR.bit.CLKRP = 0; //receives data on the falling edge of MCLKR.
McbspaRegs.RCR2.bit.RDATDLY = 1; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY = 1; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspaRegs.XCR2.bit.XPHASE = 0; //发送使用单相位帧
McbspaRegs.RCR2.bit.RPHASE = 0; //接收使用单相位帧
McbspaRegs.RCR1.bit.RWDLEN1 = 2; // 16-bit word
McbspaRegs.RCR1.bit.RFRLEN1 = 15;
McbspaRegs.XCR1.bit.XWDLEN1 = 2; // 16-bit word
McbspaRegs.XCR1.bit.XFRLEN1 = 15;
McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
McbspaRegs.SRGR1.bit.CLKGDV = 8; //10 CLKG frequency = LSPCLK/(CLKGDV+1)
McbspaRegs.SPCR2.bit.GRST = 1; // Enable the sample rate generator
//delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST = 1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST = 1; // Release RX from Reset
delay_loop();
McbspaRegs.SPCR2.bit.FRST = 1; // Frame Sync Generator reset
发送数据:
for(i=0;i<16;i++)
{
McbspaRegs.DXR1.all = Send_Dat[i];
while( McbspaRegs.SPCR1.bit.RRDY == 1 )
read_data[i] = McbspaRegs.DRR1.all;
}
不知道是不是配置问题,望赐教,先谢谢了! |