输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。
1、搜索出数据流中的帧同步字信号，并给出帧同步标志。
2、系统工作开始后，要连续3次确认帧同步字进入锁定状态后才输出帧同步标志。
3、在锁定状态时，如连续出现3次错误的帧同步字，则帧同步标志输出无效，系统重新进入搜索状态；否则继续输出有效的帧同步标志。
主程序
module test(clk,data,flag);
output reg flag;
input clk;
input[7:0] data;
parameter s0 = 3'b000,s1 = 3'b001,s2 = 3'b010,s3 = 3'b011,s4 = 3'b100, s5 = 3'b101,s6 = 3'b110,s7 = 3'b111;
parameter FF = 8'hFF;
reg[2:0] state,next_state;
reg[7:0] data_1,data_2;
reg i;
always @(posedge clk)
begin
data_2<=data;
end
always @ (posedge clk)
state<= next_state;
always @ (posedge clk)
case(state)
s0:
if(data_1== FF)
next_state<= s1;
else
next_state<= s2;
s1:
if(data_1== FF)
next_state<= s3;
else
next_state<= s2;
s2:begin
next_state<= s0;
end
s3:
if(data_1== FF)
next_state<= s4;
else
next_state<= s2;
s4:
if(data_1== FF)
next_state<= s4;
else
next_state<= s5;
s5:
if(data_1== FF)
next_state<= s4;
else
next_state<= s6;
s6:
if(data_1== FF)
next_state<= s4;
else
next_state<= s7;
s7:
if(data_1== FF)
next_state<= s1;
else
next_state<= s2;
default:
next_state<= s0;
endcase
always @ (posedge clk)
case(state)
s0:
begin
i<= 0;
data_1<= data_2;
flag<= 0;
end
s1:
begin
i<= i + 10;
data_1<= data_2;
flag<= 0;
end
s2:
begin
i<= i + 1;
data_1<= data_2;
flag<= 0;
end
s3:
begin
i<= i + 10;
data_1= data_2;
flag<= 0;
end
s4:
begin
i<= i + 10;
data_1<= data_2;
flag <= 1;
end
s5:
begin
i<= i + 10;
data_1<= data_2;
flag<= 1;
end
s6:
begin
i<= i + 10;
data_1<= data_2;
flag<= 1;
end
s7:
begin
i<= i + 10;
data_1<= data_2;
flag<= 0;
end
default:
begin
i<=0;
flag<=0;
end
endcase
endmodule
testbench
`timescale 1 ps/ 1 ps
module test_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg[7:0] data_v[99:0];
reg clk;
reg[7:0] data;
// wires
wire flag;
integer j;
// assign statements (if any)
test i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.data(data),
.flag(flag)
);
initial
begin
$readmemh("test.txt",data_v);
j<=0;
clk<=0;
end
always #10 clk=~clk;
always @(posedge clk)
begin
data[7:0]<=data_v[j];
j<=j+1;
end
endmodule
输入的数据都没有，我是设置了一个800位的数据，一个时钟上升沿读8位，不知道我这种方式对不对，哪里出问题了，求大神指教啊！！！ |
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