我有，给你贴出来吧。
// divider.v
module divider12(clock,reset,word1,word2,Start,quotient,remainder,Ready,Error);
parameter L_divn = 12;
parameter L_divr = 6;
parameter S_idle = 0,S_Adivr = 1,S_Adivn = 2,S_div = 3,S_Err = 4;
parameter L_state = 3,L_cnt = 5,Max_cnt = L_divn-L_divr;
parameter s1 = 1;
input[L_divn-1:0] word1;
input[L_divr-1:0] word2;
input clock,reset,Start;
output[L_divn-1:0] quotient;
output[L_divn-1:0] remainder;
output Ready,Error;
reg output_state,next_output_state;
reg[L_state-1:0] state,next_state;
reg Load_words,Subtract,Shift_dividend,Shift_divisor;
reg[L_divn-1:0] quotient,quotient_reg,remainder_reg;
reg[L_divn:0] dividend;
reg[L_divr-1:0] divisor;
reg[L_cnt-1:0] num_shift_dividend,num_shift_divisor;
reg[L_divr:0] comparison;
wire MSB_divr = divisor[L_divr-1];
wire Ready = ((state==S_idle)&&!reset);
wire Error = (state==S_Err);
wire Max = (num_shift_dividend==Max_cnt+num_shift_divisor);
wire sign_bit = comparison[L_divr];
always@(state or dividend or divisor or MSB_divr)
begin
case(state)
S_Adivr:if(MSB_divr == 0)
comparison = dividend[L_divn:L_divn-L_divr]+{1'b1,~(divisor<<1)}+1'b1;
else
comparison = dividend[L_divn:L_divn-L_divr]+{1'b1,~(divisor[L_divr-1:0])}+1'b1;
default: comparison = dividend[L_divn:L_divn-L_divr]+{1'b1,~(divisor[L_divr-1:0])}+1'b1;
endcase
end
assign remainder_reg = (dividend[L_divn-1:L_divn-L_divr])-num_shift_divisor;
always@(posedge clock)
begin
if(reset)begin
state <= S_idle;
output_state <= s1;
end
else begin
state <= next_state;
output_state <= next_output_state;
end
end
always@(state or word1 or word2 or comparison or sign_bit or Max)
begin
Load_words = 0;
Shift_dividend = 0;
Shift_divisor = 0;
Subtract = 0;
case(state)
S_idle:case(Start)
0:next_state = S_idle;
1:if(word2 == 0)
next_state = S_Err;
else if(word1)
begin
next_state = S_Adivr;
Load_words = 1;
end
else
next_state = S_idle;
endcase
S_Adivr:case(MSB_divr)
0:if(sign_bit == 0)
begin
next_state = S_Adivr;
Shift_divisor = 1;
end
else if(sign_bit == 1)
begin
next_state = S_Adivn;
end
1:next_state = S_div;
endcase
S_Adivn:case({Max,sign_bit})
2'b00:next_state = S_div;
2'b01:
begin
next_state = S_Adivn;
Shift_dividend = 1;
end
2'b10:
begin
next_state = S_idle;
Subtract = 1;
end
2'b11:
next_state = S_idle;
endcase
S_div:case({Max,sign_bit})
2'b00:begin
next_state = S_div;
Subtract = 1;
end
2'b01:
next_state = S_Adivn;
2'b10:begin
next_state = S_div;
Subtract = 1;
end
2'b11:begin
next_state = S_div;
Shift_dividend = 1;
end
endcase
default:next_state = S_Err;
endcase
end
always@(posedge clock)
begin
if(reset)
begin
divisor <=0;
dividend <=0;
quotient_reg <=0;
num_shift_dividend <=0;
num_shift_divisor <=0;
end
else if(Load_words == 1)begin
dividend <= word1;
divisor <= word2;
quotient_reg <=0;
num_shift_dividend <= 0;
num_shift_divisor <= 0;
end
else if(Shift_divisor)
begin
divisor <= divisor<<1;
num_shift_divisor <= num_shift_divisor+1;
end
else if(Shift_dividend)
begin
dividend <= dividend<<1;
quotient_reg <= quotient<<1;
num_shift_dividend <= num_shift_dividend+1;
end
else if(Subtract)
begin
dividend[L_divn:L_divn-L_divr] <=comparison;
quotient_reg[0] <= 1;
end
end
always@(Ready or output_state)begin
case(output_state)
s1:case(Ready)
0:next_output_state = s1;
1:begin
quotient = quotient_reg;
remainder = remainder_reg;
end
endcase
default:next_output_state = s1;
endcase
end
endmodule |
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