用VHDL编写的16—4优先编码器（8-3优先编码器级联）编译时提示错误！代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY encoder IS
PORT(d:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
e1:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gs:OUT STD_LOGIC;
e0:OUT STD_LOGIC);
END encoder;
ARCHITECTURE struc OF encoder IS
COMPONENT encoder8 --对要调用元件encoder8界面端口进行定义
PORT(d:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
e1:IN STD_LOGIC;
dq:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
gs:OUT STD_LOGIC;
e0:OUT STD_LOGIC);
END COMPONENT;
SIGNAL sink :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL aa,bb :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL carry_out,temp: STD_LOGIC;
BEGIN
U1: encoder8
PORT MAP(e1=>e1,d=>d(15 DOWNTO 8),dq=>aa(2 DOWNTO 0),e0=>CARRY_OUT,gs=>temp);
U2: encoder8
PORT MAP(e1=>carry_out,d=>d(7 DOWNTO 0),e0=>e0,gs=>gs,dq=>bb(2 DOWNTO 0));
sink(3)<=NOT temp;
sink(2)<=aa(2) NAND bb(2);
sink(1)<=aa(1) NAND bb(1);
sink(0)<=aa(0) NAND bb(0);
q<=sink(3)&sink(2)&sink(1)&sink(0);
set project ro current file 了！我的max是学生使用版的？要是那位大侠有更好的程序也可…… |
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