module key_count(
clk,
reset,
key,
a,b,c,d
);
input clk;
input reset;
input key;
output a,b,c,d;
reg a,b,c,d;
reg [3:0] key_num;
always @( posedge clk or negedge key or negedge reset )
begin
if(!key)
begin
key_num <= key_num + 4'b0001;
end
if(!reset)
begin
key_num <= 4'b0000;
{a,b,c,d} <= 4'b0000;
end
case(key_num)
4'b0000 : {a,b,c,d} <= 4'b0000;
4'b0001 : {a,b,c,d} <= 4'b0001;
4'b0010 : {a,b,c,d} <= 4'b0010;
4'b0011 : {a,b,c,d} <= 4'b0011;
4'b0100 : {a,b,c,d} <= 4'b0100;
default : {a,b,c,d} <= 4'b0000;
endcase
end
endmodule
在综合的时候出现这样的提示:The logic for d does not match a standard flip-flop
请问这是什么原因啊?
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