最近做一个FPGA的小项目，用到NIOS2软核和DDR2内核。昨天编译DDR2内核的时候遇到一个错误：
Error: The DDIO_OUT WYSIWYG primitive "nios_osd_v20:inst|altmemddr:the_altmemddr|altmemddr_controller_phy:altmemddr_controller_phy_inst|altmemddr_phy:altmemddr_phy_inst|altmemddr_phy_alt_mem_phy:altmemddr_phy_alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_e4h:auto_generated|ddio_outa[0]" feeding the pin "DDR_CK[0]" has multiple fan-outs
昨晚找了一晚，一直查不出原因。刚刚在国外的一个网站上终于找到了答案:)有几个人跟我遇到同样的问题，最后原因很简单。
“The error was not a bug in Quartus II 7.2 beta, but an error in my own design.... I had not noticed that the sdram_clk and the sdram_clk_n are both bidirectional. When this error is fixed the design compiles. I have not tested the design on my board yet, but hopefully everything works....
Regards
Tom”
开始大家都怀疑是版本的问题，后来一位兄弟找到了原因。DDR2内核的mem_clk和mem_clk_n都是双向的，而我在配置的时候把它们都设成输出了。在这里把它共享出来，希望以后遇到这个问题的朋友可以看到。 |
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