ENTITY clkdiv IS
PORT(clk : IN STD_LOGIC;
clk_div6 : OUT STD_LOGIC);
END clk_div;
ARCHITECTURE rtl OF clk_div IS
SIGNAL count : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL clk_temp : STD_LOGIC;
BEGIN
PROCESS(clk)
BEGIN
IF (clk’event AND clk=’1’) THEN
IF(count=”10”) THEN
count <= (OTHERS =>’0’);
clk_temp <=NOT clk_temp;
ELSE
count <= count +1;
END IF ;
END IF ;
END PROCESS;
clk_div6 <= clk_temp;
END rtl;
哪一段程序实现产生占空比是1：1的分频信号??????还有哪里看他实现了多少分频???大神们解释下分频器这个东东 |
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楼主
