PROTEL DRC 错误最多显示多少？

只看该作者 · 2010-6-21 08:49

Protel Design System Design Rule Check
PCB File : Documents\LT.Pcb
Date    : 21-Jun-2010
Time    : 08:56:16
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Rule Violations :0
Processing Rule : Width Constraint (Min=10mil) (Max=40mil) (Prefered=10mil) (On the board )
Violation       Polygon Arc (61070mil,57800mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (60630mil,57770mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (60630mil,57770mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (60590mil,57730mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (60631.8mil,57568.2mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (60631.8mil,57568.2mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (60590mil,57730mil)  TopLayer  Actual Width = 8mil
。。。。。。。

Violation       Polygon Arc (57020mil,57080mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (56530mil,57230mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (56530mil,57230mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (56730mil,57110mil)  TopLayer  Actual Width = 8mil
Violation       Polygon Arc (56730mil,57110mil)  TopLayer  Actual Width = 8mil
Rule Violations :500
Processing Rule : Clearance Constraint (Gap=8mil) (On the board ),(On the board )
Rule Violations :0
Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0
More than 500 violations detected. DRC stopped!
Violations Detected : 501
Time Elapsed       : 00:00:06

违反规则不是500个吗？怎么后来又说多于500，501.。这个问题严重吗？