参考一下(VHDL语言,来自百度)
--======================================
-- Decoder
--======================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dec3_8 is
port (
din : in std_logic_vector(2 downto 0) ;
dout : out std_logic_vector(7 downto 0) ;
);
end dec3_8 ;
architecture RTL of dec3_8 is
begin
dout <= "10000000" when ( din = "111" ) else
"01000000" when ( din = "110" ) else
"00100000" when ( din = "101" ) else
"00010000" when ( din = "100" ) else
"00001000" when ( din = "011" ) else
"00000100" when ( din = "010" ) else
"00000010" when ( din = "001" ) else
"00000001" ;
end RTL ;
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