/****************************************************************************
* [url=home.php?mod=space&uid=288409]@file[/url] main.c
* [url=home.php?mod=space&uid=895143]@version[/url] V2.0
* $Revision: 1 $
* $Date: 16/06/22 10:09a $
* @brief
* Measure AVDD voltage by ADC.
*
* @note
* Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "NUC123.h"
#define PLL_CLOCK 72000000
#define VBG_VOLTAGE (1200) /* 1.20V = 1200 mV (Typical band-gap voltage) */
#define ADC_SAMPLE_COUNT 128 /* The last line of GetAVDDCodeByADC() need revise when ADC_SAMPLE_COUNT is changed. */
/* For example, if ADC_SAMPLE_COUNT is changed to 64, then the code need revised to "return (u32Sum >> 6);" */
/*---------------------------------------------------------------------------------------------------------*/
/* Define Function Prototypes */
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void);
void UART0_Init(void);
void AdcMeasureAVDD(void);
uint32_t GetAVDDCodeByADC(void);
uint32_t GetAVDDVoltage(void);
/*---------------------------------------------------------------------------------------------------------*/
/* Define global variables and constants */
/*---------------------------------------------------------------------------------------------------------*/
volatile uint8_t g_u8ADF;
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable XT1_OUT(PF.0) and XT1_IN(PF.1) */
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
/* Enable external XTAL 12MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable ADC module clock */
CLK_EnableModuleClock(ADC_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_PLL, CLK_CLKDIV_UART(1));
/* ADC clock source is 22.1184MHz, set divider to 7, ADC clock is 22.1184/7 MHz */
CLK_SetModuleClock(ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_CLKDIV_ADC(7));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD;
}
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
void UART0_Init()
{
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, 115200);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: GetAVDDVoltage */
/* */
/* Parameters: */
/* None. */
/* */
/* Returns: */
/* AVDD voltage(mV). */
/* */
/* Description: */
/* Use Band-gap voltage to calculate AVDD voltage */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t GetAVDDVoltage(void)
{
uint32_t u32ConversionResult;
uint64_t u64MvAVDD;
/* Calculate Vref by using conversion result of VBG */
u32ConversionResult = GetAVDDCodeByADC();
/* u32ConversionResult = VBG * 1024 / Vref, Vref = AVDD */
/* => AVDD = VBG * 1024 / u32ConversionResult */
u64MvAVDD = (VBG_VOLTAGE << 10) / (uint64_t)u32ConversionResult;
printf("Conversion result: 0x%X\n", u32ConversionResult);
return (uint32_t)u64MvAVDD;
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: GetAVDDCodeByADC */
/* */
/* Parameters: */
/* None. */
/* */
/* Returns: */
/* ADC code of AVDD voltage. */
/* */
/* Description: */
/* Get ADC conversion result of Band-gap voltage. */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t GetAVDDCodeByADC(void)
{
uint32_t u32Count, u32Sum, u32Data;
/* Configure ADC: single-end input, single scan mode, enable ADC analog circuit. */
ADC_Open(ADC, NULL, ADC_ADCR_ADMD_SINGLE, BIT7);
/* Configure the analog input source of channel 7 as internal band-gap voltage */
ADC_CONFIG_CH7(ADC, ADC_ADCHER_PRESEL_INT_BANDGAP);
/* Power on ADC */
ADC_POWER_ON(ADC);
/* Clear conversion finish flag */
ADC_CLR_INT_FLAG(ADC, ADC_ADF_INT);
/* Enable ADC conversion finish interrupt */
ADC_EnableInt(ADC, ADC_ADF_INT);
NVIC_EnableIRQ(ADC_IRQn);
g_u8ADF = 0;
u32Sum = 0;
/* sample times are according to ADC_SAMPLE_COUNT definition */
for(u32Count = 0; u32Count < ADC_SAMPLE_COUNT; u32Count++)
{
/* Delay for band-gap voltage stability */
CLK_SysTickDelay(100);
/* Start A/D conversion */
ADC_START_CONV(ADC);
u32Data = 0;
/* Wait conversion done */
while(g_u8ADF == 0);
g_u8ADF = 0;
/* Get the conversion result */
u32Data = ADC_GET_CONVERSION_DATA(ADC, 7);
/* Sum each conversion data */
u32Sum += u32Data;
}
/* Disable ADC interrupt */
ADC_DisableInt(ADC, ADC_ADF_INT);
/* Disable ADC */
ADC_POWER_DOWN(ADC);
/* Return the average of ADC_SAMPLE_COUNT samples */
return (u32Sum >> 7);
}
/*---------------------------------------------------------------------------------------------------------*/
/* ADC interrupt handler */
/*---------------------------------------------------------------------------------------------------------*/
void ADC_IRQHandler(void)
{
uint32_t u32Flag;
/* Get ADC conversion finish interrupt flag */
u32Flag = ADC_GET_INT_FLAG(ADC, ADC_ADF_INT);
/* Check ADC conversion finish */
if(u32Flag & ADC_ADF_INT)
g_u8ADF = 1;
/* Clear conversion finish flag */
ADC_CLR_INT_FLAG(ADC, u32Flag);
}
/*---------------------------------------------------------------------------------------------------------*/
/* MAIN function */
/*---------------------------------------------------------------------------------------------------------*/
main(void)
{
uint32_t u32AVDDVoltage;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/*---------------------------------------------------------------------------------------------------------*/
/* SAMPLE CODE */
/*---------------------------------------------------------------------------------------------------------*/
printf("\nSystem clock rate: %d Hz\n", SystemCoreClock);
printf("+----------------------------------------------------------------------+\n");
printf("| ADC for AVDD Measurement sample code |\n");
printf("+----------------------------------------------------------------------+\n");
printf("\nIn this sample code, software will get voltage value from AVDD.\n");
/*------------------------------------------------------------------------------------------------------------------
The method of measured AVDD voltage is using ADC to get conversion result of band-gap voltage.
For example, the typical value of band-gap voltage is 1.20 V, and Vref of ADC is from AVDD.
Through getting ADC conversion result of band-gap voltage, then AVDD voltage can be calculated by below formula:
ConversionResult = VBG * 1024 / Vref, Vref = AVDD and VBG = 1.20V
=> AVDD = 1.20V * 1024 / ConversionResult
Note 1 : The measured AVDD has deviation that causes by the band-gap voltage has deviation in different temperature, power voltage and ADC conversion deviation.(4 LSB)
The deviation of measured AVDD is list as follows:
The Spec. of band-gap voltage in NUC123 series is as follows:
-----------------------------------------------------------------------------------------
| | Min. | Typ. | Max. | |
| |--------------------------- VDD = 2.5 V ~ 5.5 V |
| band-gap voltage | 1.18 V | 1.20 V | 1.22 V | temperature = -40 ~ 110 degrees Celsius |
| | | | | |
-----------------------------------------------------------------------------------------
Deviation range of measured AVDD
----------------------------------------------------
| | Min. Deviation | Max. Deviation |
| | | |
| | VBG = 1.18 V | VBG = 1.22 V |
|--------------------------------------------------|
| AVDD = 2.5 V | -4.57% | 4.86% |
|--------------------------------------------------|
| AVDD = 5.5 V | -7.85% | 8.98% |
----------------------------------------------------
Note 2: The typical value of band-gap voltage can be modified by VBG_VOLTAGE definition.
------------------------------------------------------------------------------------------------------------------*/
/* Measure AVDD */
u32AVDDVoltage = GetAVDDVoltage();
printf("AVDD Voltage: %dmV\n", u32AVDDVoltage);
/* Disable ADC module */
ADC_Close(ADC);
/* Disable ADC IP clock */
CLK_DisableModuleClock(ADC_MODULE);
/* Disable External Interrupt */
NVIC_DisableIRQ(ADC_IRQn);
printf("\nExit ADC sample code\n");
while(1);
}
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