module hc74hc164 (clk , en , clear , in, data);
input clk ,in , en , clear;
output [7:0] data;
reg [7:0] data;
always @ (posedge clk)
begin
if(!clear)
begin
data<=8'h0; //
end
else if(en)
begin
//data<={data , in};
data[7:0] <= {data[6:0] , in};
//$disply("data=%h\n");
end
end
endmodule
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楼主
