我用VHDL写的子程序在canvas上连接，CMD_PC ，CMD_XC为外部信号，为什么我编译时会有这两个警告?呢？把这两个信号给优化掉了呢？
Warning: Top level port CMD_PC is not connected to any IO pad
Warning: Top level port CMD_XC is not connected to any IO pad
是不是信号如果要判断边沿要在Libero里面设置某些约束？感觉与XILINX,ALTERA,LATTIACE的差别很大。
按道理来说canvas原理图连接上时有着两个信号。
说明，这两个信号我要用到边沿判断，如下程序
entity PC is
Port
(
CMD : Out std_logic_vector (15 downto 0);
CLKIN : In std_logic;--时钟
L2 : In std_logic;
L1 : In std_logic;
L0 : In std_logic;
CMD_XC : In std_logic; --信号
CMD_PC : In std_logic; --信号
CMDEN : In std_logic
);
end PC;
............................................
process(CLKIN)
begin
if(CLKIN'event and CLKIN='1') then
CMD_buf <= CMD_XC
............................................
process(CMD_XC,CMD_PC)
begin
if(PCM_XC='1') then
buf1 <= '1';
elsif(CMD_PC'event and CMD_PC='1') then
buf1 <='0';
.................................... |
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