本帖最后由 sherry88 于 2010-8-25 11:02 编辑
| Xilinx培训资料2010 之 memory | Interfacing DDR3 and LPDDR with the Spartan®-6 Hard Memory Controller
1.Understand Spartan-6 FPGA memory connectivity
advantages
– Maximize speed
– Minimize effort
– Minimize resource usage
– Minimize power
2. Learn
– Capabilities of the Spartan-6 FPGA Memory
Controller Block (MCB)
– Advantages of DDR3 and LPDDR
– Tools required to complete a design
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xfest_memory_v1.0.part1.rar
(1.91 MB)
xfest_memory_v1.0.part2.rar
(508.97 KB)
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