| 【转】modelsim和foundation ise共同工作矛盾的解决经验 | 我用的是ise 4.1i，modelsim5.5d，用网卡作为license的
来源。安装modelsim的时候选择full版。
在foundation调用modelsim之前不能打开modelsim，否则会
说:can't obtain VHDL license(我用的是VHDL）。
用modelsim之前先要编译xilinx的library，具体方法如下：
If the above TCL script did not work, you can run the commands in the
ModelSim GUI by hand. (Instructions for this follow; copy each command
and paste onto the command line in ModelSim.)
ModelSim has extended the TCL language with some simulation commands
so that TCL can be used as a scripting language to run ModelSim.
STEP 1:
These environment variable settings are provided for convenience; you do
not have to type the full path every time. If you skip this step,
just type in the full path in place of the "$" variables.
- Set access to the MODEL_TECH and XILINX environment variable:
set MODEL_TECH $env(MODEL_TECH)
set XILINX $env(XILINX)
- VERILOG_DESTN - Location for compiled Verilog libraries. This can be
any directory you wish. (The provided path is recommended.) Make sure
the directory exists before proceeding.
set VERILOG_DESTN [file join $MODEL_TECH/xilinx/verilog]
- VHDL_DESTN - Location for compiled VHDL libraries
set VHDL_DESTN [file join $MODEL_TECH/xilinx/vhdl]
STEP 2:
If you want logical library names to be available for all designs, set
your MODELSIM environment variable to the location of your master .ini
file, for example:
setenv MODELSIM $MODEL_TECH/Xilinx/modelsim.ini
If MODELSIM is not set when VMAP is run, the logical library mapping
is done locally; therefore, all VMAP commands would have to be run for
each new HDL design.
STEP 3:
For Verilog users, the compilation commands that need to be executed
are:
SimPrim:
vlib $VERILOG_DESTN/simprims
vmap simprims_ver $VERILOG_DESTN/simprims
vlog -work simprims_ver $XILINX/verilog/src/simprims/*.v
LogiBLOX:
Uses the SimPrim-based library.
UniSim:
vlib $VERILOG_DESTN/uni3000
vmap uni3000 $VERILOG_DESTN/uni3000
vlog -work uni3000 $XILINX/verilog/src/uni3000/*.v
vlib $VERILOG_DESTN/unisims_ver
vmap unisims_ver $VERILOG_DESTN/unisims_ver
vlog -work unisims_ver $XILINX/verilog/src/unisims/*.v
vlib $VERILOG_DESTN/uni5200
vmap uni5200 $VERILOG_DESTN/uni5200
vlog -work uni5200 $XILINX/verilog/src/uni5200/*.v
vlib $VERILOG_DESTN/uni9000
vmap uni9000 $VERILOG_DESTN/uni9000
vlog -work uni9000 $XILINX/verilog/src/uni9000/*.v
CORE Generator:
Please see (Xilinx Answer 8066).
----------------------------------------------------------------------
NOTE: To reference these libraries during Verilog simulation, the -L
switch must be specified during VSIM execution to specify the library
name given for the VMAP command.
Example for Verilog timing simulation:
vlog testbench.v time_sim.v glbl.v
vsim -L simprims_ver testbench_module_name glbl
----------------------------------------------------------------------
Example for VHDL timing simulation:
SimPrim:
vlib $VHDL_DESTN/simprim
vmap simprim $VHDL_DESTN/simprim
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd
LogiBLOX:
vlib $VHDL_DESTN/logiblox
vmap logiblox $VHDL_DESTN/logiblox
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd
UniSim (Versions A1.4 and later):
vlib $VHDL_DESTN/unisim
vmap unisim $VHDL_DESTN/unisim
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd
vlib $VHDL_DESTN/unisim_5k
vmap unisim_5k $VHDL_DESTN/unisim_5k
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd
CORE Generator:
Please see (Xilinx Answer 8066).
上面是xilinx的网站上的problem solver的一篇**，注意的是先要将xilinx目录下的
VHDL copy到modelsim/win32/xilinx目录下（xilinx目录自己建立）。然后就是编译了。
(因为xilinx有些库是没有的，所以有一两个命令会报错）
|
|
楼主
标题置顶
标题高亮
