是初始化的问题吗？

只看该作者 · 2010-9-19 10:42

本帖最后由 andyany 于 2010-9-20 09:16 编辑

有一个模块，单独综合没有问题。
作为子模块时，整个工程综合就出现了下面的问题。
WARNING:Xst:1710 - FF/Latch  <addr_reg_7> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_6> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_5> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_4> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_3> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_2> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_1> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1710 - FF/Latch  <addr_reg_0> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_11> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_10> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_9> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_8> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_7> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_6> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_5> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_4> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_3> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_2> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_1> (without init value) has a constant value of 0 in block <mytxd>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_reg_0> (without init value) has a constant value of 0 in block <mytxd>.
该模块是：
module mytxd(       input       clkin,
                                    input  [11:0] data_read,
                                    output [ 7:0] addr_read,
                                    output reg txd );

reg             clk_bps;
reg [ 3:0] num = 5'd0;
reg [ 9:0] cnt = 10'd0;
reg [11:0] data_reg;

reg [ 7:0] addr_reg;

assign addr_read = addr_reg;

parameter period_cnt = 10'd275;

always @ (negedge clkin)
      if(cnt == period_cnt)begin
            cnt <= 10'd0;
            clk_bps <= 1'b1; end
      else       begin
            cnt <= cnt+10'd1;
            clk_bps <= 1'b0; end

always @ (negedge clkin)
      if (clk_bps)begin
      num <= num+5'd1;
      case (num)
      5'd0:             txd <= 1'b1;
      5'd1:             txd <= 1'b0;
      5'd2:             txd <= data_reg[0];
      5'd3:       txd <= data_reg[1];
      5'd4:       txd <= data_reg[2];
      5'd5:       txd <= data_reg[3];
      5'd6:       txd <= data_reg[4];
      5'd7:             txd <= data_reg[5];
      5'd8:       txd <= data_reg[6];
      5'd9:             txd <= data_reg[7];
      5'd10:       txd <= 1'b1;
      5'd11:       txd <= 1'b0;
      5'd12:       txd <= data_reg[8];
      5'd13:       txd <= data_reg[9];
      5'd14:       txd <= data_reg[10];
      5'd15:       txd <= data_reg[11];
      5'd16:       txd <= 1'b0;
      5'd17:       txd <= 1'b0;
      5'd18:       txd <= 1'b0;
      default: begin       txd <= 1'b0;
                                             if(addr_read < 8'd166) begin
                                                      addr_reg <= addr_reg + 8'd1;
                                                      data_reg  <= data_read;
                                                      num <= 5'd0;                                        end       end
      endcase
      end

endmodule
高手们，指点一下吧！！！
谢谢！！！