想法是编写一个寄存器，通过总线收发数据。但是总线确不知道是定义成wire还是reg型的。编译的时候报错：v(19): (vlog-2110) Illegal reference to net "bus
源代码如下：
`timescale 1ns/1ns
module register( bus, enout, load,clk );
inout [7:0]bus;
input load, enout, clk;
wire [7:0]bus;
reg [7:0]inside;
initial
begin
inside <= 8'b000_0000;
end
always @( posedge clk )
begin
if ( load )
begin
inside <= bus;
end
else if ( enout )
begin
bus <= inside;
end
end
endmodule |
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