最近一直在做CY7C68013数据传输项目，目的是为了将FPGA开发板产生的随机数信号通过USB接口传至PC机，目前Bulkloop.c代码修改过了，fifo_wr.v也写好了，但是写入开发板后，EZ-USB的pipe不对，因为我设置的是EP2 IN 但是界面显示EP2 OUT 不知道哪里代码哪里修改错了，希望大佬指点。附上Bulkloop.c的代码和fifo_wr.v的代码。
//-----------------------------------------------------------------------------
// File: bulkloop.c
// Contents: Hooks required to implement USB peripheral function.
//
// $Archive: /USB/Examples/FX2LP/bulkloop/bulkloop.c $
//
//
//-----------------------------------------------------------------------------
// Copyright (c) 2011, Cypress Semiconductor Corporation All rights reserved
//-----------------------------------------------------------------------------
#pragma NOIV // Do not generate interrupt vectors
#include "..\inc\fx2.h"
#include "..\inc\fx2regs.h"
#include "..\inc\syncdly.h" // SYNCDELAY macro
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
#define VR_NAKALL_ON 0xD0
#define VR_NAKALL_OFF 0xD1
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz, Default 12MHz(Page 333)
//CPUCS = 0x02; //12MHZ CLKOUT ENALBE
//CPUCS = 0x0a; //24MHZ CLKOUT ENALBE
CPUCS = 0x12; //48MHZ CLKOUT ENALBE，时钟不反向，CLKOUT PIN驱动，有时钟输出；
SYNCDELAY;
//Interface Configure(Page 334)
IFCONFIG =0x03; //选择为外部时钟，且时钟频率为30MHz，且为同步slaveFIFO模式,输入IFCLK(5~48MHz)(0000_0011)
//IFCONFIG =0x0B;//选择为外部时钟，且为异步slaveFIFO模式,不需要IFCLK
SYNCDELAY;
//Configure REVCTL for Chip Revision Control(Page 344)
REVCTL = 0x03; //Cypress highly recommends setting both bits to 1
SYNCDELAY;
Rwuen = TRUE; // Enable remote-wakeup
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIF**SEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
// we are just using the default values, yes this is not necessary...
EP1OUTCFG = 0xA0;
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xE0;
SYNCDELAY;
EP4CFG = 0x60; // disabled...
SYNCDELAY;
EP6CFG = 0x60; // disabled...
SYNCDELAY;
EP8CFG = 0x60; // disabled...
//=========================大大的分割线=================================//
//复位FIFO,先复位端点，再清空端点(Page 340)
SYNCDELAY;
FIFORESET = 0x80;// activate NAK-ALL to avoid race conditions
SYNCDELAY;
FIFORESET = 0x02;// reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x04;// reset, FIFO 4
SYNCDELAY;
FIFORESET = 0x06;// reset, FIFO 6
SYNCDELAY;
FIFORESET = 0x08;// reset, FIFO 8
SYNCDELAY;
FIFORESET = 0x00;// deactivate NAK-AL
SYNCDELAY;
//Configure the EPxFIFOCFG(Page 349)
EP2FIFOCFG = 0x08; // autoin, 8 Bit Wide,0000_1000 自动使能IN
// EP2FIFOCFG = 0x09; // autoin, 16 Bit Wide
SYNCDELAY;
EP4FIFOCFG = 0x00; // no-autoOUT, bytewide
SYNCDELAY;
EP6FIFOCFG = 0x00; // no-autoOUT, bytewide
SYNCDELAY;
EP8FIFOCFG = 0x00; // no-autoOUT, bytewide
SYNCDELAY;
//--------------------------------------------------------
//Configure PIN Polarity
PORTACFG = 0x40; //IFCOG[1:0] = 11(Slave FIFO Mode), Set PORTACFG[6] to USE PA7-SLCS (Page 275) 0100_0000
SYNCDELAY;
FIFOPINPOLAR = 0x04; //BIT[5:0] = {PKTEND, SLOE, SLRD, SLWR, EMPTY, FULL}--0000_0100
//Set SLWR High Valid; PKTEND，SLOE，SLRD EMPTY, FULL Low Active(Page 342)
SYNCDELAY;
//--------------------------------------------------------
//设置为Autoin时的自动传输包大小(Page 239)
SYNCDELAY;
EP2AUTOINLENH = 0x02; // EZ-USB automatically commits data in 512-byte chunks 0000_0010
// EP2AUTOINLENH = 0x04; // EZ-USB automatically commits data in 1024-byte chunks
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;
//Set Autopointer, enable dual autopointer(Page 215-216)
AUTOPTRSETUP = 0x01;
//FLAGA - User-Programmable Level; FLAGB - FIFO Full, FLAGC - FIFO Empty: (L: Valid)(Page 223)
PINFLAGSAB = 0x00;//0x8a;
SYNCDELAY;
PINFLAGSCD = 0x00;//0x08;
SYNCDELAY;
//===========================大大的分割线===============================//
/*
// out endpoints do not come up armed
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP4BCL = 0x80; // arm EP4OUT by writing byte count w/skip.
SYNCDELAY;
EP4BCL = 0x80;
*/
// enable dual autopointer feature
//AUTOPTRSETUP |= 0x01;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
AlternateSetting = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
BOOL DR_VendorCmnd(void)
{
BYTE tmp;
switch (SETUPDAT[1])
{
case VR_NAKALL_ON:
tmp = FIFORESET;
tmp |= bmNAKALL;
SYNCDELAY;
FIFORESET = tmp;
break;
case VR_NAKALL_OFF:
tmp = FIFORESET;
tmp &= ~bmNAKALL;
SYNCDELAY;
FIFORESET = tmp;
break;
default:
return(TRUE);
}
return(FALSE);
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures(void) interrupt 0
{
// whenever we get a USB reset, we should revert to full speed mode
pConfigDscr = pFullSpeedConfigDscr;
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
pOtherConfigDscr = pHighSpeedConfigDscr;
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
EZUSB_IRQ_CLEAR();
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp(void) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUSP;
}
void ISR_Highspeed(void) interrupt 0
{
if (EZUSB_HIGHSPEED())
{
pConfigDscr = pHighSpeedConfigDscr;
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
pOtherConfigDscr = pFullSpeedConfigDscr;
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
Verilog--fifo_wr.v
module fifo_wr(
clk ,
rst_n ,
//Other signal
//input
fifo_full ,//flag
load ,
// fifo_empty ,//flag
//output
fifo_wr ,//fifo_wr signal
fifo_data ,//fifo write data
fifoadr //select fifo
);
//参数定义
parameter DATA_W = 8;
parameter STATE_W = 3;
parameter IDLE = 0;
parameter S1 = 1;
parameter S2 = 2;
parameter S3 = 3;
parameter S4 = 4;
//输入信号定义
input clk ;
input rst_n ;
input fifo_full ;
input load ;
//input fifo_empty ;
//输出信号定义
output fifo_wr ;
output[DATA_W-1:0] fifo_data ;
output[2-1:0] fifoadr ;
//输出信号reg定义
reg fifo_wr ;
reg [DATA_W-1:0] fifo_data ;
reg [2-1:0] fifoadr ;
//中间信号定义
reg clkin ;
reg [STATE_W-1:0] state_c ;
reg [STATE_W-1:0] state_n ;
wire start_s3 ;
wire end_s4 ;
wire [DATA_W-1:0] rand_num;
//First div clk by 2
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
clkin <= 'b1;
end
else begin
clkin<= ~clkin;
end
end
//三段式状态机
//第一个进程，同步时序always模块，格式化描述次态寄存器迁移到现态寄存器(不需更改）
always@(posedge clkin or negedge rst_n)begin
if(!rst_n)begin
state_c <= IDLE;
end
else begin
state_c <= state_n;
end
end
//第二个进程，组合逻辑always模块，描述状态转移条件判断
always@(*)begin
case(state_c)
IDLE:begin
state_n = S1;
end
S1:begin
state_n = S2 ;
end
S2:begin
if(start_s3)begin
state_n = S3;
end
else begin
state_n = state_c;
end
end
S3:begin
state_n = S4;
end
S4:begin
if(end_s4)begin
state_n = S2;
end
else begin
state_n = IDLE;
end
end
default:begin
state_n = IDLE;
end
endcase
end
//assign start_s1 = state_c==IDLE && ;
assign start_s3 = state_c==S2 && fifo_full;
assign end_s4 = state_c==S3 && fifo_full;
//assign end_s2 = state_c==S2 && ;
//第三个进程，同步时序always模块，格式化描述寄存器输出（可有多个输出）
//fifoadr 此处应该考虑写状态fifoadr和非写状态的fifoadr是不一样的
always @(posedge clkin or negedge rst_n)begin
if(rst_n==1'b0 )begin
fifoadr <= 2'b 10;
end
else begin
fifoadr <= 2'b 10;//10指的是EP6
end
//else if(state_c==S1)begin
// fifoadr <= 2'b00;//目前还不知道具体选哪个
// end
end
//fifo_wr
always @(posedge clkin or negedge rst_n)begin
if(!rst_n)begin
fifo_wr <=1'b0; //初始化
end
else if(state_c==S3)begin
fifo_wr <= 1'b1;
end
else begin
fifo_wr <= 1'b0;
end
end
//fifo_data
always @(posedge clkin or negedge rst_n)begin
if(rst_n==1'b0)begin
fifo_data <= 'hff;
end
else if(state_c == S3)begin
fifo_data <= rand_num ;
end
end
//例化RanGen
RanGen uut_RanGen(
.clk (clk ),
.rst_n (rst_n ),
.load (load ),
.rand_num (rand_num)
);
endmodule
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