最近在改一块S3C4510的板子的RAM;但是看了两天没弄明白芯片的SDRAM是如何工作的.
s3c4510B网上流行的SDRAM接口是用的两片 HY57V641620 并联构建32 位的 SDRAM 存储器系统；将两片 HY57V641620 作为一个整体配置到DRAM/SDRAM Bank0
HY57V641620 的Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7；而s3c4510的地址总线有23条，分时复用，产生行列地址的时候式怎么确定范围的？
比如说CPU是怎么知道SDRAM的Row Address是RA0 ~ RA11而不是RA0 ~ RA22呢？需要设置哪里东西？期待高手指点！
//=========================================================================================================
下面是s3c4510B所支持的SDRAM：（两片 HY57V641620 并联构建32 位的 SDRAM 存储器系统是否属于“— 4Mx16 with 4banks (supported) RA0–
RA11,CA0–CA7”）
Available Samsung SDRAM Components for S3C4510B
Components
S3C4510B can support below SDRAM configuration for 1 bank.
· 2MBytes to 1 bank ® 1 ´ (2Mx32 with 4banks)
· 4MBytes to 1 bank ® 2 ´ (1Mx16 with 2banks)
· 8MBytes to 1 bank ® 4 ´ (2Mx8 with 2banks)
· 16MBytes to 1bank ® 2 ´ (4Mx16 with 2/4banks)
· 32MBytes to 1bank ® 4 ´ (8Mx8 with 2/4banks)
You can select any combination among them.
SDRAM components that are available are as follow.
x4 SDRAM whose capacity is larger than 16M SDRAM is not supported at S3C4510B.
16M bit SDRAM
— 4Mx4 with 2banks (Supported) RA0–RA10, CA0–CA9
— 2Mx8 with 2banks (Supported) RA0–RA10, CA0–CA8
— 1Mx16 with 2banks (Supported) RA0–RA10, CA0–CA7
64M bit 2Banks SDRAM
— 16Mx4 with 2banks (not supported) RA0–RA12, CA0–CA9
— 8Mx8 with 2banks (supported) RA0–RA12, CA0–CA8
— 4Mx16 with 2banks (supported) RA0–RA12, CA0–CA7
64M bit 4Banks SDRAM
— 16Mx4 with 4banks (not supported) RA0–RA11, CA0–CA9
— 8Mx8 with 4banks (supported) RA0–RA11, CA0–CA8
— 4Mx16 with 4banks (supported) RA0–RA11, CA0–CA7
2Mx32 (64M bit) SDRAM
— 2Mx32 with 4banks (supported) RA0–RA10, CA0–CA7
100 Pin DIMM Module SDRAM
KMM330S104CT
— 1Mx32 based on 2 1Mx16 2banks components RA0–RA10, CA0–CA7
KMM330S204CT
— 4Mx32 based on 4 1Mx16 2banks components RA0–RA10, CA0–CA7
KMM330S2424CT
— 4Mx32 based on 2 4Mx16 4banks componets RA0–RA11, CA0–CA7
KMM330S824CT
— 8Mx32 based on 4 4Mx16 4banks componets RA0–RA11, CA0–CA7
|
楼主
标题置顶
标题高亮
