本人是Verilog HDL入门者,在MAX+plus II编译下列程序时,出现这样一个错误:
Error:Line1,File e:\adder4.tdf:
TDF syntax error:Expected ASSERT,CONSTANT,DEFINE,DESIGN,FUNCTION,
IF,POTIONS,PARAMETERS,SUBDESIGN,or TITLE but found a symbolic name"module"
原程序如下:module adder4(cout,sum,ina,inb,cin);
output[3:0] sum;
output cout;
input[3:0] ina,inb;
input cin;
assign {cout,sum}=ina+inb+cin;
endmodule
本人不知道错在哪里,找不出问题来,请高手们指点,谢谢! |