哥,我写的是这个,可是仿真出来后led值一直不变,是哪儿错了吗?
module led_water(clk,rst,led
);
input clk;
input rst;
output reg [3:0] led;
reg [25:0] counter;
parameter T=26'd49999999;
always@(negedge rst or posedge clk)
if(!rst)
begin
counter<=26'd0;
led<=4'b1110;
end
else
begin
if(counter==T)
begin
led<={led[2:0],led[3:0]};
counter<=26'd0;
end
else
begin
led<=led;
counter<=counter+26'd1;
end
end
endmodule |