ADSP-BF561 DMA方式介绍
9 Direct Memory Access
9 直接内存访问（DMA）
The processor uses Direct Memory Access (DMA) to transferdata within memory spaces or between a memory space and a peripheral. Theprocessor can specify data transfer operations and return to normal processingwhile the fully integrated DMA controller carries out the data transfersindependent of processor activity
处理器用DMA方式在存储器之间或者存储器与外围设备之间传递数据。在完全集成的DMA控制器独立于处理器活动传输数据的同时，处理器能够识别出数据传输操作然后返回到正常处理工作。
ADSP-BF561 has three independent DMA controllers, DMA1, DMA2and IMDMA. The centralized DMA control configurations with variable sized datastructure descriptors are capable of data transfers within memories or betweenmemory and a peripheral. Each of DMA1 and DMA2 has twelve peripheral DMAchannels and four memory DMA channels. IMDMA has four memory DMA channels.
ADSP-BF561 有三个独立的DMA控制器，DMA1, DMA2 和 IMDMA。
中央DMA控制结构能够在内存之间或者内存与外围设计之间传递数据并且它具有一个不定大小数据结构的描述符是。DMA1和DMA2各有十二个外围DMA通道，四个存储器DMA通道。IMDMA有四个存储器DMA通道。
Note: Peripherals connected to theDMA1 controller can support up to 32-bit data transfers, while those connectedto DMA2 can support up to 16-bit transfers. For more information, refer to “ChipBus Hierarchy”
注意：连接到DMA1的外围设备能够支持32位的数据传输，连接到DMA2的外围设备支持16位。想了解更多信息请查阅“芯片总线结构”。
·
The DMA controllers can perform several types ofdata transfers:
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Between internal memories (L1/L2) (IMDMA, MDMA1,MDMA2) Chapter 6, “Memory.”
·
Between external memory (SDRAM, Flash memory)and internal memory (L1/L2) (MDAM1, MDMA2) chapter 6, “Memory.”
·
Between memory and the Serial PeripheralInterface (SPI) Chapter 10, “SPI compatible Port Controllers.”
·
Between memory and a Serial Port (SPORT) Chapter12, “Serial Port Controllers.”
·
Between memory and the UART Port Chapter 13, “UARTPort Controller.”
·
Between memory and the Parallel PeripheralInterface (PPI) Chapter 11, “Parallel Peripheral Interface.”
DMA 控制器的数据传输方式：
·
内部存储器（L1/L2）（IMDMA, MDMA1, MDMA2）之间。第6章，“存储器”。
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外部存储器（SDRAM, Flash memory）与内部存储器（L1/L2）（MDMA1,MDMA2）之间。第6章，“存储器”。
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存储器与串行外围设备接口（SPI）之间。第10章，“SPI 兼容接口控制器”。
·
存储器与串口（SPORT）之间。第12章，“串行接口控制器”。
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存储器与UART接口之间
。第13章，“UART 接口控制器”。
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存储器与并行外围设备接口（PPI）之间。第11章，“并行外围设备接口”。
Table 9-1 shows the default channel assignment at DSP reset.The channel number is also the default channel priority number; a value of 0indicates the highest priority. However, the user can program it using thePeripheral Map Register(DMAx_PERIPHERAL_MAP or MDMA_yy_PERIPHERAL_MAP).
表9-1说明了在DSP复位时默认的管道分配。管道编号也是管道的默认优先级，0代表最高优先级。但是，用户可以通过外围设备映射寄存器（DMAx_PERIPHERAL_MAP或DMA_yy_PERIPHERAL_MAP）来修改优先级。
Table 9-1. DefaultChannel Assignment DMA1
| Description
| DMA2
| Description
| IMDMA
| Description
| Channel0
| PPI0 Receive/Transmit
| Channel0
| SPORT0 Receive
| Channel0
| IMDMA Stream0 Destination
| Channel1
| PPI1 Receive/Transmit
| Channel1
| SPORT0 Transmit
| Channel1
| IMDMA Stream0 Source
| Channel2
| Reserved
| Channel2
| SPORT1 Receive
| Channel2
| IMDMA Stream1 Destination
| Channel3
| Reserved
| Channel3
| SPORT2 Transmit
| Channel3
| IMDMA Stream1 Source
| Channel4
| Reserved
| Channel4
| SPI Receive/Transmit
|
|
| Channel5
| Reserved
| Channel5
| UART Receive
|
|
| Channel6
| Reserved
| Channel6
| UART Transmit
|
|
| Channel7
| Reserved
| Channel7
| Reserved
|
|
| Channel8
| Reserved
| Channel8
| Reserved
|
|
| Channel9
| Reserved
| Channel9
| Reserved
|
|
| Channel10
| Reserved
| Channel10
| Reserved
|
|
| Channel11
| Reserved
| Channel11
| Reserved
|
|
| Channel12
| MDMA Stream0 Destination
| Channel12
| MDMA Stream0 Destination
|
|
| Channel13
| MDMA Stream0 Source
| Channel13
| MDMA Stream0 Source
|
|
| Channel14
| MDMA Stream1 Destination
| Channel14
| MDMA Stream1 Destination
|
|
| Channel15
| MDMA Stream1
Source
| Channel15
| MDMA Stream1 Source
|
|
|
This Chapter describes the features common to all the DMAchannels, as well as how DMA operations are set up. For specific peripheralfeatures, see the appropriate peripheral chapter for additional information.Performance and bus arbitration for DMA can be found in “DAB, DCB, and DEBPerformance” on another page.
这一章描述了所有DMA通道的公共特征以及如何设置DMA操作。如果想了解详细而精确的外围设备特征，可查阅与外围设备对应的相关章节。DMA的性能及总线仲裁在其他页面的“DAB,DCB和DEB性能”中可以找到。
DMA transfers on the processor can be descriptor-based orregister-based. Descriptor-based DMA transfers require a set of parametersstored within memory to initiate a DMA sequence. This sort of transfer allowsthe chaining together of multiple DMA sequences. In descriptor-based DMAoperation, a DMA channel can be programmed to automatically set up and startanother DMA transfer after the current sequence completes. Register-based DMAallows the processor to directly program DMA control registers to initiate aDMA transfer. On completion, the control registers may be automatically updatedwith their original setup values for continuous transfer, if needed.
处理器上的DMA传输可以使基于描述符或者基于寄存器的。基于描述符的DMA传输需要存储器中的参数集来启动DMA序列。这种传输方法允许多个DMA队列链接在一起。在基于描述符的DMA操作中，可以通过编程使DMA自动设置并且在当前队列完成以后开始下一个DMA传输。基于寄存器的DMA允许处理器直接通过修改DMA控制寄存器来启动DMA传输。当传输完成时，如果需要的话，控制寄存器可能会自动更新为原始设置并继续传输。
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