我是第一次用modelsim altera6.5B仿真，一直都是出现这种情况，请大侠们帮我解决一下，我实在是搞不定了
Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./compare_run_msim_rtl_verilog.do PAUSED at line 12
vsim work.compare_vlg_tst
# vsim work.compare_vlg_tst
# ** Error: Failure to obtain a Verilog simulation license.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./compare_run_msim_rtl_verilog.do PAUSED at line 12
vsim work.compare_vlg_tst
# vsim work.compare_vlg_tst
# ** Error: Failure to obtain a Verilog simulation license. |
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