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Protel Design System Design Rule Check<br />PCB File : Documentsxin.PCB<br />Date : 15-Oct-2007<br />Time : 09:46:18<br /><br />Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )<br /> Violation between Pad R3-1(9515.185mil,11038.685mil) TopLayer and <br /> Arc (9515.185mil,11032.28mil) TopLayer <br /> (8548.022mil,10837.578mil)(8583.8mil,10801.8mil) TopLayer and <br /> Pad C7-1(8584.2mil,10801.4mil) TopLayer <br /> 9341.354mil,10130mil) TopLayer <br /> Violation between Track (9202.2mil,10141.2mil)(9266.149mil,10141.2mil) TopLayer and <br /> Pad T8-1(9266.354mil,10130mil) TopLayer <br /> Violation between Track (9266.354mil,10051.752mil)(9266.354mil,10138.965mil) TopLayer and <br /> Pad T8-1(9266.354mil,10130mil) TopLayer <br /> <br /> Pad T5-2(9343mil,10261.6mil) TopLayer <br />Rule Violations :173<br /><br />Processing Rule : Broken-Net Constraint ( (On the board ) )<br />Rule Violations :0<br /><br />Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )<br />Rule Violations :0<br /><br />Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )<br /> Violation Polygon Arc (9720.472mil,11232.65mil) TopLayer Actual Width = 8mil<br /> <br /> Violation Polygon Arc (8494.354mil,9932.965mil) TopLayer A (8665.029mil,10722.375mil) TopLayer Actual Width = 8mil<br /> Violation Polygon Arc (8778.354mil,11162.965mil) TopLayer Actual Width = 8mil<br />Rule Violations :327<br /><br />Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )<br />Rule Violations :0<br /><br />More than 500 violations detected. DRC stopped!<br /><br />Violations Detected : 501<br /> |
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