Protel Design System Design Rule Check
PCB File : Documentsxin.PCB
Date : 15-Oct-2007
Time : 09:46:18
Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Violation between Pad R3-1(9515.185mil,11038.685mil) TopLayer and
Arc (9515.185mil,11032.28mil) TopLayer
(8548.022mil,10837.578mil)(8583.8mil,10801.8mil) TopLayer and
Pad C7-1(8584.2mil,10801.4mil) TopLayer
9341.354mil,10130mil) TopLayer
Violation between Track (9202.2mil,10141.2mil)(9266.149mil,10141.2mil) TopLayer and
Pad T8-1(9266.354mil,10130mil) TopLayer
Violation between Track (9266.354mil,10051.752mil)(9266.354mil,10138.965mil) TopLayer and
Pad T8-1(9266.354mil,10130mil) TopLayer
Pad T5-2(9343mil,10261.6mil) TopLayer
Rule Violations :173
Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Rule Violations :0
Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )
Violation Polygon Arc (9720.472mil,11232.65mil) TopLayer Actual Width = 8mil
Violation Polygon Arc (8494.354mil,9932.965mil) TopLayer A (8665.029mil,10722.375mil) TopLayer Actual Width = 8mil
Violation Polygon Arc (8778.354mil,11162.965mil) TopLayer Actual Width = 8mil
Rule Violations :327
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Rule Violations :0
More than 500 violations detected. DRC stopped!
Violations Detected : 501
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