请问一下关于verilog赋值出现问题

timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 19:48:31 11/05/2017

// Design Name:

// Module Name: decoding

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 – File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module decoding(clk,In,Xout_VGA,Yout_VGA,Out,Ready,Xout_VGA_F,Yout_VGA_F,Rout,Cout);

input clk;

input [7:0]In;

output reg [9:0]Xout_VGA;//X输出VGA

output reg [9:0]Yout_VGA;//Y输出VGA

output reg [9:0]Xout_VGA_F;//Y输出VGA目的地

output reg [9:0]Yout_VGA_F;//Y输出VGA目的地

output reg [7:0]Out;//输出

output reg [4:0]Ready;//0为数据,1为D,2为.,3为X,4为Y,5为x,6为y,7为R,8为C，9为负号

output reg[1:0]Rout;//=1记录

output reg[1:0]Cout;//=1清除



reg [1:0]Reading;//数据读取

reg [1:0]XsReading;//小数读取标识

reg [1:0]Sign;//1为正，0为负

reg [9:0]Cache;//整数和整体数据缓冲

reg [1:0]Count;//计数

//D-12.34XD56.78Y

initial

begin

Reading=0;

Cache=0;

Count=1;

XsReading=0;

Rout=0;

Cout=0;

end



always [url=home.php?mod=space&uid=72445]@[/url] (posedge clk)

begin

Rout<=0;

Cout<=0;

Ready<=0;

if(In==68)//D

begin

Reading<=1;

Ready<=1;

XsReading<=0;

end

if(In==45)//-

begin

Sign<=0;

Ready<=9;

end

if(In==46)//.

begin

XsReading<=1;

Ready<=2;

end

if(In==88||In==89||In==120||In==121)//X,x,Y,y

begin

Reading<=0;

if(In==88)

begin

Ready<=3;

end

if(In==89)

begin

Ready<=4;

end

if(In==120)

begin

Ready<=5;

end

if(In==121)

begin

Ready<=6;

end

end

if(In==82||In==67)//R或者C

begin

Reading<=0;

XsReading<=0;

if(In==82)

begin

Ready<=7;

Rout<=1;

end

if(In==67)

begin

Ready<=8;

Cout<=1;

end

end

end



always @ (posedge clk)

begin

//整数数据读取

if(Reading==1&&XsReading==0&&In!=68&&Count==1&&In!=45)//第一位

begin

Cache<=In-48;

Out<=Cache[7:0];

Cache<=(Cache*10);

Count<=2;

end

else if(Reading==1&&XsReading==0&&In!=68&&Count==2&&In!=45)//第二位

begin

Cache<=(Cache+In-48);

Out<=In-48;

Count<=1;

end

//小数

if(Reading==1&&XsReading==1&&In!=68&&In!=45)

begin

Out<=In-48;

end



//输出为负数

if(In==88&&Sign==0)

begin

Cache<=464-Cache*2;

Xout_VGA<=Cache;

Cache<=0;

end

else if(In==89&&Sign==0)

begin

Cache<=274+Cache*2;

Yout_VGA<=Cache;

Cache<=0;

end

else if(In==120&&Sign==0)

begin

Cache<=464-Cache*2;

Xout_VGA_F<=Cache;

Cache<=0;

end

else if(In==121&&Sign==0)

begin

Cache<=274+Cache*2;

Yout_VGA_F<=Cache;

Cache<=0;

end

//输出,为正数

if(In==88&&Sign==1)

begin

Cache<=464+Cache*2;

Xout_VGA<=Cache;

Cache<=0;

end

else if(In==89&&Sign==1)

begin

Cache<=274-Cache*2;

Yout_VGA<=Cache;

Cache<=0;

end

else if(In==120&&Sign==1)

begin

Cache<=464+Cache*2;

Xout_VGA_F<=Cache;

Cache<=0;

end

else if(In==121&&Sign==1)

begin

Cache<=274-Cache*2;

Yout_VGA_F<=Cache;

Cache<=0;

end



end

endmodule

f(Reading==1&&XsReading==0&&In!=68&&Count==1&&In!=45)//第一位

begin

Cache<=In-48;

Out<=Cache[7:0];

Cache<=(Cache*10);

Count<=2;

end