用verilog描述BCD码加法器逢十进一
module add_4bcd(cout,sum,ina,inb,cin);
input cin;input[3:0] ina,inb;
output[3:0] sumreg[3:0] sum;
output cout;reg cout;
reg[4:0] temp;
always @(ina,inb,cin)
begin temp<=ina+inb+cin;
if(temp>9){cout,sum}<=temp+6;
else{cout,sum}<=temp;
end
endmodule
中
if(temp>9){cout,sum}<=temp+6;这句话是什么意思？？小弟新手！！！ |
楼主
