初学modelsim，却遇此般挫折，请教各路大神

只看该作者 · 2018-2-12 16:04

如图，编写完testbench后，modelsim仿真一直加载不出信号，检查修改testbench多次以后也没能得到正确结果，想问大佬们是怎么解决这类问题的。
以下附testbench代码.

***********************************************************************************************
`timescale 1ns/1ps
module mux21_tb();

//==============================================================================
localparam PERIOD = 10; //100M
reg eachvec;
//==============================================================================
//build clk
reg clk, rst_n;

initial
begin
clk = 0;
forever #(PERIOD/2) clk = ~clk;
end

//------------------------------------
//reset signal
task task_reset;
begin
rst_n = 0;
repeat(2) @(negedge clk);
rst_n = 1;
end
endtask

//------------------------------------
//initial mux21
reg                a;
reg                b;
reg                s;
wire                c;

mux21 u_mux21
(
.clk          (clk),
.a             (a),
.b             (b),
.s             (s),
.c             (c)
);

//------------------------------------
//task of input
task task_test;
input       a1;
input       b1;
input       s1;
begin
a <= a1;
b <= b1;
s <= s1;
end
endtask

//------------------------------------
//testbench of RTL
initial
begin
task_sysinit;
task_reset;

task_test(0, 0, 0);

repeat (5) @(posedge clk);
task_test(1, 0, 0);

repeat (5) @(posedge clk);
task_test(0, 1, 0);

repeat (5) @(posedge clk);
task_test(1, 1, 0);

repeat (5) @(posedge clk);
task_test(0, 0, 1);

repeat (5) @(posedge clk);
task_test(0, 1, 1);

repeat (5) @(posedge clk);
task_test(1, 0, 1);

repeat (5) @(posedge clk);
task_test(1, 1, 1);
end

endmodule